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[83.52.54.50]) by smtp.gmail.com with ESMTPSA id a82sm2213204wmc.45.2020.09.01.07.41.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 07:41:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 3/4] hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields Date: Tue, 1 Sep 2020 16:40:59 +0200 Message-Id: <20200901144100.116742-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200901144100.116742-1-f4bug@amsat.org> References: <20200901144100.116742-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This model implementation is designed for 32-bit accesses. We can simplify setting the MemoryRegionOps::impl min/max fields to 32-bit (memory::access_with_adjusted_size() will take care of the 8/16-bit accesses). Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/a9scu.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c index 3f3dcc414fe..47f948341f7 100644 --- a/hw/misc/a9scu.c +++ b/hw/misc/a9scu.c @@ -28,12 +28,6 @@ static uint64_t a9_scu_read(void *opaque, hwaddr offset, return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); case 0x08: /* CPU Power Status */ return s->status; - case 0x09: /* CPU status. */ - return s->status >> 8; - case 0x0a: /* CPU status. */ - return s->status >> 16; - case 0x0b: /* CPU status. */ - return s->status >> 24; case 0x0c: /* Invalidate All Registers In Secure State */ return 0; case 0x40: /* Filtering Start Address Register */ @@ -52,8 +46,6 @@ static void a9_scu_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { A9SCUState *s = (A9SCUState *)opaque; - uint32_t mask = MAKE_64BIT_MASK(0, size * 8); - uint32_t shift; switch (offset) { case 0x00: /* Control */ @@ -62,9 +54,7 @@ static void a9_scu_write(void *opaque, hwaddr offset, case 0x4: /* Configuration: RO */ break; case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ - shift = (offset - 0x8) * 8; - s->status &= ~(mask << shift); - s->status |= ((value & mask) << shift); + s->status = value; break; case 0x0c: /* Invalidate All Registers In Secure State */ /* no-op as we do not implement caches */ @@ -84,6 +74,10 @@ static void a9_scu_write(void *opaque, hwaddr offset, static const MemoryRegionOps a9_scu_ops = { .read = a9_scu_read, .write = a9_scu_write, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, .valid = { .min_access_size = 1, .max_access_size = 4,