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[83.52.54.50]) by smtp.gmail.com with ESMTPSA id b2sm5325802wmh.47.2020.09.03.10.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 10:28:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/4] hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses Date: Thu, 3 Sep 2020 19:28:04 +0200 Message-Id: <20200903172806.489710-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200903172806.489710-1-f4bug@amsat.org> References: <20200903172806.489710-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Prasad J Pandit , qemu-block@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Alexander Bulekov , qemu-arm@nongnu.org, Ruhr-University Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" If we have pending DMA requests scheduled, process them first. So far we don't need to implement a bottom half to process them. Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 703357e94a7..2b197631870 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -945,11 +945,21 @@ sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) return true; } +static void sdhci_resume_pending_transfer(SDHCIState *s) +{ + timer_del(s->transfer_timer); + sdhci_data_transfer(s); +} + static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) { SDHCIState *s = (SDHCIState *)opaque; uint32_t ret = 0; + if (timer_pending(s->transfer_timer)) { + sdhci_resume_pending_transfer(s); + } + switch (offset & ~0x3) { case SDHC_SYSAD: ret = s->sdmasysad; @@ -1093,6 +1103,10 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) uint32_t value = val; value <<= shift; + if (timer_pending(s->transfer_timer)) { + sdhci_resume_pending_transfer(s); + } + switch (offset & ~0x3) { case SDHC_SYSAD: s->sdmasysad = (s->sdmasysad & mask) | value;