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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id r22sm2540856pfg.51.2020.10.27.07.08.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2020 07:09:00 -0700 (PDT) From: Bin Meng X-Google-Original-From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Date: Tue, 27 Oct 2020 22:08:33 +0800 Message-Id: <20201027140840.18030-3-bin.meng@windriver.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201027140840.18030-1-bin.meng@windriver.com> References: <20201027140840.18030-1-bin.meng@windriver.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x544.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Atish Patra , Anup Patel , Ivan Griffin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. Signed-off-by: Bin Meng --- hw/riscv/Kconfig | 1 + hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++ include/hw/riscv/microchip_pfsoc.h | 5 +++++ 3 files changed, 24 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2df978fe8d..c8e50bde99 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -4,6 +4,7 @@ config IBEX config MICROCHIP_PFSOC bool select CADENCE_SDHCI + select MCHP_PFSOC_DMC select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4627179cd3..85be2bcde8 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -15,6 +15,7 @@ * 4) Cadence eMMC/SDHC controller and an SD card connected to it * 5) SiFive Platform DMA (Direct Memory Access Controller) * 6) GEM (Gigabit Ethernet MAC Controller) + * 7) DMC (DDR Memory Controller) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -85,7 +86,9 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, @@ -131,6 +134,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "dma-controller", &s->dma, TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, + TYPE_MCHP_PFSOC_DDR_SGMII_PHY); + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, + TYPE_MCHP_PFSOC_DDR_CFG); + object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); @@ -260,6 +268,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); + /* DDR SGMII PHY */ + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, + memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); + + /* DDR CFG */ + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, + memmap[MICROCHIP_PFSOC_DDR_CFG].base); + /* SDHCI */ sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 8bfc7e1a85..5b81e26241 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -24,6 +24,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" +#include "hw/misc/mchp_pfsoc_dmc.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; + MchpPfSoCDdrCfgState ddr_cfg; MchpPfSoCMMUartState *serial0; MchpPfSoCMMUartState *serial1; MchpPfSoCMMUartState *serial2; @@ -82,7 +85,9 @@ enum { MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_DDR_SGMII_PHY, MICROCHIP_PFSOC_EMMC_SD, + MICROCHIP_PFSOC_DDR_CFG, MICROCHIP_PFSOC_MMUART1, MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3,