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[209.51.188.17]) by mx.google.com with ESMTPS id k5si3135990ybp.301.2021.02.10.14.56.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 10 Feb 2021 14:56:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="gR/uZKib"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l9yPG-0002bM-Am for patch@linaro.org; Wed, 10 Feb 2021 17:56:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l9xqS-00071Q-Dd for qemu-devel@nongnu.org; Wed, 10 Feb 2021 17:20:28 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:53848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l9xqI-0006rY-OJ for qemu-devel@nongnu.org; Wed, 10 Feb 2021 17:20:23 -0500 Received: by mail-wm1-x32f.google.com with SMTP id j11so3203819wmi.3 for ; Wed, 10 Feb 2021 14:20:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HGyTKfyrMC02NQIDciJuv0x1b/kxlzbJP/1nTgEUSN0=; b=gR/uZKibyVFlrqalLm+DNQ7QTCzXkJqMl4ixYc8w1+ZU1CYThBDMbBUo5Bh97jxceH olwGv99ZTFoQxukoCi35pUBZNvvjRCzPOvLso6tcMNys0I3QIqx5zM2UmjXe0x2qQeKd lyba2kcKoDUN9jhFa29MbjHBwUMSL4to3qU2wwAHrp+rojFhFdVvbIOxO9lcYH1Ttc9O qdkjuEwok/xGKcoFXVVM/kUrbY/j/M7Zn993+zS5vcJFLQ+lATMuhMgAr/AJMyfkFop8 /zwEjKO+oRo2QNoR6+OICuGFYi20TJ8aU3eea5IfzVp77HCUrMVkE7+Q4ZiRMhozorvs ZICw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HGyTKfyrMC02NQIDciJuv0x1b/kxlzbJP/1nTgEUSN0=; b=WNbnQQdn03YIq/Ns1ySLaBsKmCQwKHiVnBUatUJkYnxXoXyC652/e+tfcyQ07fknJc TMIe10GX/U4Z+6lSvKDycDbMrOlN88ADsCr5rL9wOsC5YgwoYgNcWtsULgQ1QjWI1jNm aXGtsFqr0WgQzFRuZ1U/eKA5OkCESYIV5CvMINZ+t3JqZfFaA/Ot2ZGpuidipuAvT17D +rgbmXeA3ti2aP5wc+f9IfQh/ITahVCj1VvxueWlXZ2D9QqO+DkxnZnCaGYmykZlBYfG YX/Bd6Mxgyh1mjISfFIgz5EnxSCpklo9YMMmkTQ3+ALqrEnOHQsc7C87C9zHZMZq56FT HXKA== X-Gm-Message-State: AOAM531pm7IMGTFoQVCE6RLWaYXxoncLq9HMJx7dW1bw35GIciCi/mbB CTOX0aLnRQNFzjIKSi8c5mBDjg== X-Received: by 2002:a1c:f203:: with SMTP id s3mr1219378wmc.152.1612995613038; Wed, 10 Feb 2021 14:20:13 -0800 (PST) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 17sm4871093wmf.32.2021.02.10.14.20.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 14:20:12 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2AD7C1FF9F; Wed, 10 Feb 2021 22:10:55 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v2 16/21] accel/tcg: actually cache our partial icount TB Date: Wed, 10 Feb 2021 22:10:48 +0000 Message-Id: <20210210221053.18050-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210210221053.18050-1-alex.bennee@linaro.org> References: <20210210221053.18050-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , robhenry@microsoft.com, mahmoudabdalghany@outlook.com, aaron@os.amperecomputing.com, cota@braap.org, Paolo Bonzini , kuhn.chenqun@huawei.com, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When we exit a block under icount with instructions left to execute we might need a shorter than normal block to take us to the next deterministic event. Instead of creating a throwaway block on demand we use the existing compile flags mechanism to ensure we fetch (or compile and fetch) a block with exactly the number of instructions we need. Signed-off-by: Alex Bennée Message-Id: <20210209182749.31323-8-alex.bennee@linaro.org> --- v2 - drop pointless assert --- accel/tcg/cpu-exec.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.20.1 Reviewed-by: Richard Henderson diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d9ef69121c..5b6a4fe84b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -730,16 +730,17 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, /* Ensure global icount has gone forward */ icount_update(cpu); /* Refill decrementer and continue execution. */ - insns_left = MIN(0xffff, cpu->icount_budget); + insns_left = MIN(CF_COUNT_MASK, cpu->icount_budget); cpu_neg(cpu)->icount_decr.u16.low = insns_left; cpu->icount_extra = cpu->icount_budget - insns_left; - if (!cpu->icount_extra && insns_left < tb->icount) { - /* Execute any remaining instructions, then let the main loop - * handle the next event. - */ - if (insns_left > 0) { - cpu_exec_nocache(cpu, insns_left, tb, false); - } + + /* + * If the next tb has more instructions than we have left to + * execute we need to ensure we find/generate a TB with exactly + * insns_left instructions in it. + */ + if (!cpu->icount_extra && insns_left > 0 && insns_left < tb->icount) { + cpu->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left; } #endif }