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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id s1sm605959pfc.6.2021.05.26.21.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 21:14:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/11] target/i386: Use float_flag_inorm_denormal Date: Wed, 26 May 2021 21:13:59 -0700 Message-Id: <20210527041405.391567-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210527041405.391567-1-richard.henderson@linaro.org> References: <20210527041405.391567-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, mmorrell@tachyum.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The FSR and MXCSR DE flags have the semantics of the new flag. We get to remove a big fixme in update_mxcsr_from_sse_status vs float_flag_iflush_denormal. Reported-by: Michael Morrell Signed-off-by: Richard Henderson --- target/i386/tcg/fpu_helper.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index c9779a9fe0..edc550de55 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -148,7 +148,7 @@ static void merge_exception_flags(CPUX86State *env, uint8_t old_flags) (new_flags & float_flag_overflow ? FPUS_OE : 0) | (new_flags & float_flag_underflow ? FPUS_UE : 0) | (new_flags & float_flag_inexact ? FPUS_PE : 0) | - (new_flags & float_flag_iflush_denormal ? FPUS_DE : 0))); + (new_flags & float_flag_inorm_denormal ? FPUS_DE : 0))); } static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b) @@ -1742,7 +1742,7 @@ void helper_fxtract(CPUX86State *env) int shift = clz64(temp.l.lower); temp.l.lower <<= shift; expdif = 1 - EXPBIAS - shift; - float_raise(float_flag_iflush_denormal, &env->fp_status); + float_raise(float_flag_inorm_denormal, &env->fp_status); } else { expdif = EXPD(temp) - EXPBIAS; } @@ -2976,7 +2976,8 @@ void update_mxcsr_status(CPUX86State *env) (mxcsr & FPUS_ZE ? float_flag_divbyzero : 0) | (mxcsr & FPUS_OE ? float_flag_overflow : 0) | (mxcsr & FPUS_UE ? float_flag_underflow : 0) | - (mxcsr & FPUS_PE ? float_flag_inexact : 0), + (mxcsr & FPUS_PE ? float_flag_inexact : 0) | + (mxcsr & FPUS_DE ? float_flag_inorm_denormal : 0), &env->sse_status); /* set denormals are zero */ @@ -2989,20 +2990,13 @@ void update_mxcsr_status(CPUX86State *env) void update_mxcsr_from_sse_status(CPUX86State *env) { uint8_t flags = get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_iflush_denormal (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ env->mxcsr |= ((flags & float_flag_invalid ? FPUS_IE : 0) | (flags & float_flag_divbyzero ? FPUS_ZE : 0) | (flags & float_flag_overflow ? FPUS_OE : 0) | (flags & float_flag_underflow ? FPUS_UE : 0) | (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_oflush_denormal ? FPUS_UE | FPUS_PE : - 0)); + (flags & float_flag_inorm_denormal ? FPUS_DE : 0) | + (flags & float_flag_oflush_denormal ? FPUS_UE | FPUS_PE : 0)); } void helper_update_mxcsr(CPUX86State *env)