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[209.51.188.17]) by mx.google.com with ESMTPS id t2si16454018ybo.375.2021.06.29.12.39.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Jun 2021 12:39:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wxqldrgu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lyJZv-0004yh-JP for patch@linaro.org; Tue, 29 Jun 2021 15:39:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lyItO-0008Qt-KV for qemu-devel@nongnu.org; Tue, 29 Jun 2021 14:55:30 -0400 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]:39477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lyItA-0000uO-4L for qemu-devel@nongnu.org; Tue, 29 Jun 2021 14:55:30 -0400 Received: by mail-pf1-x42a.google.com with SMTP id g192so99734pfb.6 for ; Tue, 29 Jun 2021 11:55:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AkdZtWwj/8ggy1eq6EhClTwBg3K4IFRXh2vcItTXzCk=; b=Wxqldrguoqye5KOvfRW41fpSOsAovJ01QJAqjLSQ5W0o1NuHSVGGl2gMOoqvaXfmbE euQlIXEnJe5zvpewgWDA+gXI8SPVAdSeOaQY+5EQ9vETrmaazH8AXrDjMc52cwNdmkCN vlW/AbHrE2pqR6YSrpgd/FaNY90HQQ1jk15d4hiRuYR5giuVnDt8T+dMlPYsEcwgcweI j3q4IW4fTN14eL5mza7STLTlzw62TC1For/M75QFjLx4+EtzFZz1EUpscR6oA5s0Fj7G jXogDk8O1KUWzUVItZwBtVNw5XjsTmEc5zuGl9CcYjg9k9FGSQ3oX4urKh0RyIs+BN8A TXXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AkdZtWwj/8ggy1eq6EhClTwBg3K4IFRXh2vcItTXzCk=; b=a7jfmcPT2Zlia4UdzZNeihAGSsijqT97peSngneqjr9nJLEWQyo386NjUCJBYJRLLi Z5vQg0oYaj32uICNI255RVvn4czNpsKTcpLfp/tZujArD3kxqocov2LCcjOCmD5iD07N Cy6aUWZ4aHQNLUybBqgHIHqfzMeIjD6uCZA5RgcDGjzFIY6hp4YiKR3TTysBgWqb2y7l gMYhuwOsPXXHd8lBa/Mzy6mdN6aJ/imVfduv6L+PFp1TeB9iFeBbYoqYaaVtZqd5mOWY ZSudQVmD0oM5G2K4KAjtg3zX8DmRTIsqjk8N3/Hb+pXgNFyTzzSXJaIFKQPhq3YvRjoo z7pw== X-Gm-Message-State: AOAM532U4+yix6p8iMNRvm/YhzYCtnHi/teIzvjrx+LuUaCjFx0PkJHa cIhnzwnYOWHYPT0kmoxnsftPjz9XPqFrww== X-Received: by 2002:a63:fd0c:: with SMTP id d12mr22841592pgh.119.1624992913491; Tue, 29 Jun 2021 11:55:13 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id j2sm18811253pfb.53.2021.06.29.11.55.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Jun 2021 11:55:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/63] tcg: Add tcg_gen_vec_add{sub}8_i32 Date: Tue, 29 Jun 2021 11:54:22 -0700 Message-Id: <20210629185455.3131172-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629185455.3131172-1-richard.henderson@linaro.org> References: <20210629185455.3131172-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: LIU Zhiwei Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Implement tcg_gen_vec_add{sub}8_tl by adding corresponging i32 OP. Signed-off-by: LIU Zhiwei Message-Id: <20210624105023.3852-3-zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 6 ++++++ tcg/tcg-op-gvec.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) -- 2.25.1 diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 9b67822f54..2d5ad6ce12 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -402,14 +402,20 @@ void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); /* 32-bit vector operations. */ +void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); #if TARGET_LONG_BITS == 64 +#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64 +#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64 #define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64 #else +#define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32 +#define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32 #define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32 #endif diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 7ddd56c0e6..6d9a0aed62 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -1736,6 +1736,25 @@ void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) gen_addv_mask(d, a, b, m); } +void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80)); + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + + tcg_gen_andc_i32(t1, a, m); + tcg_gen_andc_i32(t2, b, m); + tcg_gen_xor_i32(t3, a, b); + tcg_gen_add_i32(d, t1, t2); + tcg_gen_and_i32(t3, t3, m); + tcg_gen_xor_i32(d, d, t3); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); +} + void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000)); @@ -1900,6 +1919,25 @@ void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) gen_subv_mask(d, a, b, m); } +void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 m = tcg_constant_i32((int32_t)dup_const(MO_8, 0x80)); + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + TCGv_i32 t3 = tcg_temp_new_i32(); + + tcg_gen_or_i32(t1, a, m); + tcg_gen_andc_i32(t2, b, m); + tcg_gen_eqv_i32(t3, a, b); + tcg_gen_sub_i32(d, t1, t2); + tcg_gen_and_i32(t3, t3, m); + tcg_gen_xor_i32(d, d, t3); + + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); +} + void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000));