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[209.51.188.17]) by mx.google.com with ESMTPS id 143si16307784qkk.90.2021.06.29.12.54.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Jun 2021 12:54:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nf4i6+uD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:43298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lyJoP-000480-VF for patch@linaro.org; Tue, 29 Jun 2021 15:54:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lyIwQ-00041p-IB for qemu-devel@nongnu.org; Tue, 29 Jun 2021 14:58:40 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:40917) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lyIwH-0002zE-8a for qemu-devel@nongnu.org; Tue, 29 Jun 2021 14:58:38 -0400 Received: by mail-pl1-x631.google.com with SMTP id m17so39828plx.7 for ; Tue, 29 Jun 2021 11:58:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q38h6dtquTVJ+FlY8+y6d1PvihW63oSAgr0zeRiMB4s=; b=Nf4i6+uDEyOy0dbFkTC29NvGNi6XBKyZT0IPSOlrmtHobo5Wkyrp4rsh3DolTKnJok BVmUtPx750QAZQFh1N13WWa+ySPXnrD+KKE9rxEyXZ5ftYnWcm3Oyr+7OuWSQPGcwS7C bC//FLP+1azqZHi8xaO5p0A53HFaM3F6ykuvT8OYm+KYkDzkCxgXAy87tircG4Aq/7jX /F/ti/ehcmMQ3EhAPn0/hy63pkV1rGxELZ1JJZMDRgeldcfNnXNXwRjo85MD3c9PicfX yjBGcT2flabqYk2iJdHjoqjYvAy5jfELdUhtwyualShpGuM9QAlS+jG8DlQSw06hfdoJ Gyxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q38h6dtquTVJ+FlY8+y6d1PvihW63oSAgr0zeRiMB4s=; b=p2UZfjfiP95oNCyPm3gYuwyPrLYX3QmTHwioyKe2UQ7yYu40HjYoDJmoEmo7uEA4Ay 71x1bA1zQ4LcA9KQZFteur1VNdqRUXESp2Ezy4ll89zCjYULqWIJqc01uC5LAaPZx/My 8Kguf9Iv79b0AEHmQz9jr4ajNSMbVkuvYZ3zHOdpKzodkTevfutKAJAPqWDZqZ0ho6M6 HlO5pwZQsO/SqDr9mF42662ToCUgJlHCp8bzf2+fqF840Ltiv05dJpF3To2L7fH9LRda GEjawZIjavDkBpvuDWFdxJ0AZhdNu6Qvcr9REHFsfJAJOhxXoq19YnvqU2zM2PQSkq2G nPhA== X-Gm-Message-State: AOAM530FTQ3hIfuuQtO9PtzbzTXiZ6dUXnegQVFkFhb65EFjj0OsmIRk OWM9iwpV/SgEdTVQmKXI+5KcYPqLzVHx7g== X-Received: by 2002:a17:90a:9205:: with SMTP id m5mr327093pjo.172.1624993106503; Tue, 29 Jun 2021 11:58:26 -0700 (PDT) Received: from localhost.localdomain ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id 21sm18002849pfh.103.2021.06.29.11.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Jun 2021 11:58:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 47/63] tcg/s390: Support bswap flags Date: Tue, 29 Jun 2021 11:54:39 -0700 Message-Id: <20210629185455.3131172-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210629185455.3131172-1-richard.henderson@linaro.org> References: <20210629185455.3131172-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For INDEX_op_bswap16_i64, use 64-bit instructions so that we can easily provide the extension to 64-bits. Drop the special case, previously used, where the input is already zero-extended -- the minor code size savings is not worth the complication. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc index 5fe073f09a..b82cf19f09 100644 --- a/tcg/s390/tcg-target.c.inc +++ b/tcg/s390/tcg-target.c.inc @@ -1951,15 +1951,37 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]); break; - OP_32_64(bswap16): - /* The TCG bswap definition requires bits 0-47 already be zero. - Thus we don't need the G-type insns to implement bswap16_i64. */ - tcg_out_insn(s, RRE, LRVR, args[0], args[1]); - tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16); + case INDEX_op_bswap16_i32: + a0 = args[0], a1 = args[1], a2 = args[2]; + tcg_out_insn(s, RRE, LRVR, a0, a1); + if (a2 & TCG_BSWAP_OS) { + tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16); + } else { + tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16); + } break; - OP_32_64(bswap32): + case INDEX_op_bswap16_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + tcg_out_insn(s, RRE, LRVGR, a0, a1); + if (a2 & TCG_BSWAP_OS) { + tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48); + } else { + tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48); + } + break; + + case INDEX_op_bswap32_i32: tcg_out_insn(s, RRE, LRVR, args[0], args[1]); break; + case INDEX_op_bswap32_i64: + a0 = args[0], a1 = args[1], a2 = args[2]; + tcg_out_insn(s, RRE, LRVR, a0, a1); + if (a2 & TCG_BSWAP_OS) { + tgen_ext32s(s, a0, a0); + } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { + tgen_ext32u(s, a0, a0); + } + break; case INDEX_op_add2_i32: if (const_args[4]) {