| Message ID | 20210717221851.2124573-9-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: breakpoint reorg | expand |
On Sat, 17 Jul 2021 at 23:18, Richard Henderson <richard.henderson@linaro.org> wrote: > > Since 0b00b0c1e05b, tb->size must not be zero. > Advance pc so that the breakpoint covers the insn at the bp. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/avr/translate.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/avr/translate.c b/target/avr/translate.c > index 8237a03c23..d768063d65 100644 > --- a/target/avr/translate.c > +++ b/target/avr/translate.c > @@ -2950,6 +2950,7 @@ static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, > DisasContext *ctx = container_of(dcbase, DisasContext, base); > > gen_breakpoint(ctx); > + ctx->base.pc_next += 2; /* advance by minimum insn len so tb->size != 0 */ > return true; > } Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 7/18/21 12:18 AM, Richard Henderson wrote: > Since 0b00b0c1e05b, tb->size must not be zero. > Advance pc so that the breakpoint covers the insn at the bp. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/avr/translate.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On 7/18/21 12:18 AM, Richard Henderson wrote: > Since 0b00b0c1e05b, tb->size must not be zero. > Advance pc so that the breakpoint covers the insn at the bp. > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/489 > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/avr/translate.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/avr/translate.c b/target/avr/translate.c > index 8237a03c23..d768063d65 100644 > --- a/target/avr/translate.c > +++ b/target/avr/translate.c > @@ -2950,6 +2950,7 @@ static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, > DisasContext *ctx = container_of(dcbase, DisasContext, base); > > gen_breakpoint(ctx); > + ctx->base.pc_next += 2; /* advance by minimum insn len so tb->size != 0 */ > return true; > } > >
diff --git a/target/avr/translate.c b/target/avr/translate.c index 8237a03c23..d768063d65 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2950,6 +2950,7 @@ static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, DisasContext *ctx = container_of(dcbase, DisasContext, base); gen_breakpoint(ctx); + ctx->base.pc_next += 2; /* advance by minimum insn len so tb->size != 0 */ return true; }
Since 0b00b0c1e05b, tb->size must not be zero. Advance pc so that the breakpoint covers the insn at the bp. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/avr/translate.c | 1 + 1 file changed, 1 insertion(+) -- 2.25.1