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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l38sm8158506wmp.15.2021.08.12.02.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Aug 2021 02:34:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH for-6.2 04/25] hw/timer/armv7m_systick: Add usual QEMU interface comment Date: Thu, 12 Aug 2021 10:33:35 +0100 Message-Id: <20210812093356.1946-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210812093356.1946-1-peter.maydell@linaro.org> References: <20210812093356.1946-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Luc Michel , Alistair Francis , Subbaraya Sundeep , Joel Stanley , Alexandre Iooss Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the usual-style QEMU interface comment documenting what properties, etc, this device exposes. Signed-off-by: Peter Maydell --- include/hw/timer/armv7m_systick.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.20.1 Reviewed-by: Alistair Francis Reviewed-by: Luc Michel diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h index 84496faaf96..685fc5bc0d7 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -20,6 +20,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(SysTickState, SYSTICK) +/* + * QEMU interface: + * + sysbus MMIO region 0 is the register interface (covering + * the registers which are mapped at address 0xE000E010) + * + sysbus IRQ 0 is the interrupt line to the NVIC + */ + struct SysTickState { /*< private >*/ SysBusDevice parent_obj;