From patchwork Wed Oct 6 15:20:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 515355 Delivered-To: patch@linaro.org Received: by 2002:ac0:b5cc:0:0:0:0:0 with SMTP id x12csp566738ime; Wed, 6 Oct 2021 09:12:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9hehfHkw3PSnQ/Ghh1x/sc9dUTWMy0u+FD4v/DDOA+xBx5Nnp/MtQSI4gyOjxevdyZxFV X-Received: by 2002:a37:8044:: with SMTP id b65mr20556305qkd.295.1633536725513; Wed, 06 Oct 2021 09:12:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1633536725; cv=none; d=google.com; s=arc-20160816; b=PlezVxb+GXdRJ6hHvHOdcC7IJzr1kSwbtOdee/23Z0iQkpkt74XfpKrshDhQCG9WJN LEdSoDAxxgSSwOY1aa0n/Xvc0qmZeZ//cV1UIiCDzoF4YbKtCnEMBnPDdLuA96IcCcLh bw/LfoXqRLnQO6pGoFVL9Hd8TrU7k+cllNH1H6GYN63TM8YF31HLVzfxI7D4+nn/R1O9 L9VvAFPNwpzEQo1jLpz1yPrdTUqdY1//s3LxXbCY5wdEcH/8wnXKNY5yuP0u+Hlbqp7i dMFWEi/geWsiCkLd1Taz757CWNVgz+vnXlYSUcg6snCTeeaGJTT6j0c9nzE19lKr9Owf tPjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rT+FjwD1ufCx9lnpEuLLrFv2Zrr97TNJL1CVvR401No=; b=WtMJkN00dh1WQcQqf1MT9gX9c+/arfFMBAqk4ydEaY81JOWSadJeD4HaQiS0sDUFpn Qt4goSRBEEvQI/Qlop/Ru6Tvk9+zh1XZ/czdtm39gvjNXmIXvQrY3ed1R1YSa2/J1W21 wKTWzzsMLZx19fcHPOQ5+temzpbknZs6c2Y7/ddWcV6u9BCek7v58scLsr2U9eW/aNv6 DBRpoJ73pcmbrNTJWfU/iFZEjC1OwAyWVNzGatTKGX7ZiQi1FW3QWTF7FQ2cYSogLEOb wYoTxX10M4vgYn8UMOgzJCtJykKFQZNE/ky/oNAt+hjQdaZN872RCLDUo56Och55Ttlg AmFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RnVpMnBP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jo30si13683307qvb.243.2021.10.06.09.12.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Oct 2021 09:12:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RnVpMnBP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mY9WW-0006f4-Q8 for patch@linaro.org; Wed, 06 Oct 2021 12:12:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mY8jB-0002hS-BQ for qemu-devel@nongnu.org; Wed, 06 Oct 2021 11:21:06 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:36745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mY8in-0007s2-DV for qemu-devel@nongnu.org; Wed, 06 Oct 2021 11:21:05 -0400 Received: by mail-pf1-x42b.google.com with SMTP id m26so2664560pff.3 for ; Wed, 06 Oct 2021 08:20:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rT+FjwD1ufCx9lnpEuLLrFv2Zrr97TNJL1CVvR401No=; b=RnVpMnBPGwYmVJTidP3atvFNATHLBrk3JqQAeY/K70roH328zHgFAlCzhX4pnqxN1N COOy56sNWhluUC5oBRjihNyQNXpjo7iRlewQe7MmtsXSRQQ0E/7dL+HSm3yCy/Du6jAQ enqFOOdQ4ZIgcHKOVmhlH7+05k2U2q3xM8+f0bdyS68rEBi4k0YcXnJadnVf4vToqj6O +0tJLB91o6GX2He8lqftSgpi6ilxf86ZnC71lIjK026Gwu23WmKIZqmSZbn3Nd94qeGX 7ZJWLyKUZyCg2rV88teypVFC4tMM31i7fmR0ljtwxQFH8a+Ryk8JjRKmaEIXFwQzRlPD 91mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rT+FjwD1ufCx9lnpEuLLrFv2Zrr97TNJL1CVvR401No=; b=6XWtOs6EH9K8PTlh2g+tp3FYtraYDj0H33Wb5oeUF0hi420KDfkL0ZyLywYMz/UOrn 5E8+IfrB1JFjyxtZdHoCivCjnP0PipcvwRomRchHExl29k0wxMa267ygokqxH5t69A8A qr7nLU6AQenjRIZJezi3Gfyn2Wo1hdDGamS8/fPOlf+8cgRHukQT1M4zup25EaJ2yl46 LZoKsfHh/Bxx/A3VtPOk5CwasriMmILpQ3syJzz20xZmDB5w8a7o1/ob9g+x4hTPciCL 4hlO1Ir++H7Nq04HlOd/56eVCgyPSnbJ5rAM2VUgW/aPaH6LxbA/ejoCqjlZHJ61fLq2 kbrQ== X-Gm-Message-State: AOAM530c88OqvdUXXV2OnxbDCLhgQgpdH8WKplCVq6zLZcHAHYjdnCd1 iNGtYm9St6NMJUI5Oe8C/n5p7N/I2PPidg== X-Received: by 2002:a05:6a00:16c6:b029:32d:e190:9dd0 with SMTP id l6-20020a056a0016c6b029032de1909dd0mr37064278pfc.70.1633533634125; Wed, 06 Oct 2021 08:20:34 -0700 (PDT) Received: from localhost.localdomain ([71.212.134.125]) by smtp.gmail.com with ESMTPSA id 130sm22239256pfz.77.2021.10.06.08.20.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Oct 2021 08:20:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/28] tcg/s390x: Implement tcg_out_dup*_vec Date: Wed, 6 Oct 2021 08:20:06 -0700 Message-Id: <20211006152014.741026-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211006152014.741026-1-richard.henderson@linaro.org> References: <20211006152014.741026-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 ++++++++++++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 586a4b5587..f59250872b 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,13 +265,20 @@ typedef enum S390Opcode { RX_STC = 0x42, RX_STH = 0x40, + VRIa_VGBM = 0xe744, + VRIa_VREPI = 0xe745, + VRIb_VGM = 0xe746, + VRIc_VREP = 0xe74d, + VRRa_VLR = 0xe756, + VRRf_VLVGP = 0xe762, VRSb_VLVG = 0xe722, VRSc_VLGV = 0xe721, VRX_VL = 0xe706, VRX_VLLEZ = 0xe704, + VRX_VLREP = 0xe705, VRX_VST = 0xe70e, VRX_VSTEF = 0xe70b, VRX_VSTEG = 0xe70a, @@ -563,6 +570,34 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) | ((v4 & 0x10) << (4 + 0)); } +static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, int m3) +{ + tcg_debug_assert(is_vector_reg(v1)); + tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); +} + +static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, + TCGReg v1, uint8_t i2, uint8_t i3, int m4) +{ + tcg_debug_assert(is_vector_reg(v1)); + tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4)); + tcg_out16(s, (i2 << 8) | (i3 & 0xff)); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); +} + +static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, TCGReg v3, int m4) +{ + tcg_debug_assert(is_vector_reg(v1)); + tcg_debug_assert(is_vector_reg(v3)); + tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | (v3 & 0xf)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg v2, int m3) { @@ -572,6 +607,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); } +static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg r2, TCGReg r3) +{ + tcg_debug_assert(is_vector_reg(v1)); + tcg_debug_assert(is_general_reg(r2)); + tcg_debug_assert(is_general_reg(r3)); + tcg_out16(s, (op & 0xff00) | ((v1 & 0xf) << 4) | r2); + tcg_out16(s, r3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); +} + static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, intptr_t d2, TCGReg b2, TCGReg r3, int m4) { @@ -2501,19 +2547,89 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { - g_assert_not_reached(); + if (is_general_reg(src)) { + /* Replicate general register into two MO_64. */ + tcg_out_insn(s, VRRf, VLVGP, dst, src, src); + if (vece == MO_64) { + return true; + } + } + + /* + * Recall that the "standard" integer, within a vector, is the + * rightmost element of the leftmost doubleword, a-la VLLEZ. + */ + tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); + return true; } static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset) { - g_assert_not_reached(); + tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); + return true; } static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, int64_t val) { - g_assert_not_reached(); + int i, mask, msb, lsb; + + /* Look for int16_t elements. */ + if (vece <= MO_16 || + (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { + tcg_out_insn(s, VRIa, VREPI, dst, val, vece); + return; + } + + /* Look for bit masks. */ + if (vece == MO_32) { + if (risbg_mask((int32_t)val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x80000001u) == 0x80000001u) { + msb = 32 - ctz32(~val); + lsb = clz32(~val) - 1; + } else { + msb = clz32(val); + lsb = 31 - ctz32(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32); + return; + } + } else { + if (risbg_mask(val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { + /* Handle wraparound by swapping msb and lsb. */ + msb = 64 - ctz64(~val); + lsb = clz64(~val) - 1; + } else { + msb = clz64(val); + lsb = 63 - ctz64(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64); + return; + } + } + + /* Look for all bytes 0x00 or 0xff. */ + for (i = mask = 0; i < 8; i++) { + uint8_t byte = val >> (i * 8); + if (byte == 0xff) { + mask |= 1 << i; + } else if (byte != 0) { + break; + } + } + if (i == 8) { + tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); + return; + } + + /* Otherwise, stuff it in the constant pool. */ + tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); + new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); + tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); } static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,