| Message ID | 20211015041053.2769193-12-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | user-only: Cleanup SIGSEGV and SIGBUS handling | expand |
On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson < richard.henderson@linaro.org> wrote: > Split host_signal_pc and host_signal_write out of user-exec.c. > Drop the *BSD code, to be re-created under bsd-user/ later. > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++- > accel/tcg/user-exec.c | 45 +------------------------------ > 2 files changed, 30 insertions(+), 45 deletions(-) > Reviewed-by: Warner Losh <imp@bsdimp.com> > diff --git a/linux-user/host/arm/host-signal.h > b/linux-user/host/arm/host-signal.h > index f4b4d65031..6932224c1c 100644 > --- a/linux-user/host/arm/host-signal.h > +++ b/linux-user/host/arm/host-signal.h > @@ -1 +1,29 @@ > -#define HOST_SIGNAL_PLACEHOLDER > +/* > + * host-signal.h: signal info dependent on the host architecture > + * > + * Copyright (C) 2021 Linaro Limited > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or > later. > + * See the COPYING file in the top-level directory. > + */ > + > +#ifndef ARM_HOST_SIGNAL_H > +#define ARM_HOST_SIGNAL_H > + > +static inline uintptr_t host_signal_pc(ucontext_t *uc) > +{ > + return uc->uc_mcontext.arm_pc; > +} > + > +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) > +{ > + /* > + * In the FSR, bit 11 is WnR, assuming a v6 or > + * later processor. On v5 we will always report > + * this as a read, which will fail later. > + */ > + uint32_t fsr = uc->uc_mcontext.error_code; > + return extract32(fsr, 11, 1); > +} > + > +#endif > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c > index 17fe867aeb..5656c654e1 100644 > --- a/accel/tcg/user-exec.c > +++ b/accel/tcg/user-exec.c > @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong > addr, int size, > return size ? g2h(env_cpu(env), addr) : NULL; > } > > -#if defined(__arm__) > - > -#if defined(__NetBSD__) > -#include <ucontext.h> > -#include <sys/siginfo.h> > -#endif > - > -int cpu_signal_handler(int host_signum, void *pinfo, > - void *puc) > -{ > - siginfo_t *info = pinfo; > -#if defined(__NetBSD__) > - ucontext_t *uc = puc; > - siginfo_t *si = pinfo; > -#else > - ucontext_t *uc = puc; > -#endif > - unsigned long pc; > - uint32_t fsr; > - int is_write; > - > -#if defined(__NetBSD__) > - pc = uc->uc_mcontext.__gregs[_REG_R15]; > -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && > __GLIBC_MINOR__ <= 3)) > - pc = uc->uc_mcontext.gregs[R15]; > -#else > - pc = uc->uc_mcontext.arm_pc; > -#endif > - > -#ifdef __NetBSD__ > - fsr = si->si_trap; > -#else > - fsr = uc->uc_mcontext.error_code; > -#endif > - /* > - * In the FSR, bit 11 is WnR, assuming a v6 or > - * later processor. On v5 we will always report > - * this as a read, which will fail later. > - */ > - is_write = extract32(fsr, 11, 1); > - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); > -} > - > -#elif defined(__aarch64__) > +#if defined(__aarch64__) > > #if defined(__NetBSD__) > > -- > 2.25.1 > > <div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson <<a href="mailto:richard.henderson@linaro.org">richard.henderson@linaro.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Split host_signal_pc and host_signal_write out of user-exec.c.<br> Drop the *BSD code, to be re-created under bsd-user/ later.<br> <br> Reviewed-by: Philippe Mathieu-Daudé <<a href="mailto:f4bug@amsat.org" target="_blank">f4bug@amsat.org</a>><br> Signed-off-by: Richard Henderson <<a href="mailto:richard.henderson@linaro.org" target="_blank">richard.henderson@linaro.org</a>><br> ---<br> linux-user/host/arm/host-signal.h | 30 ++++++++++++++++++++-<br> accel/tcg/user-exec.c | 45 +------------------------------<br> 2 files changed, 30 insertions(+), 45 deletions(-)<br></blockquote><div><br></div><div><div>Reviewed-by: Warner Losh <<a href="mailto:imp@bsdimp.com">imp@bsdimp.com</a>></div><br class="gmail-Apple-interchange-newline"></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"> diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h<br> index f4b4d65031..6932224c1c 100644<br> --- a/linux-user/host/arm/host-signal.h<br> +++ b/linux-user/host/arm/host-signal.h<br> @@ -1 +1,29 @@<br> -#define HOST_SIGNAL_PLACEHOLDER<br> +/*<br> + * host-signal.h: signal info dependent on the host architecture<br> + *<br> + * Copyright (C) 2021 Linaro Limited<br> + *<br> + * This work is licensed under the terms of the GNU GPL, version 2 or later.<br> + * See the COPYING file in the top-level directory.<br> + */<br> +<br> +#ifndef ARM_HOST_SIGNAL_H<br> +#define ARM_HOST_SIGNAL_H<br> +<br> +static inline uintptr_t host_signal_pc(ucontext_t *uc)<br> +{<br> + return uc->uc_mcontext.arm_pc;<br> +}<br> +<br> +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc)<br> +{<br> + /*<br> + * In the FSR, bit 11 is WnR, assuming a v6 or<br> + * later processor. On v5 we will always report<br> + * this as a read, which will fail later.<br> + */<br> + uint32_t fsr = uc->uc_mcontext.error_code;<br> + return extract32(fsr, 11, 1);<br> +}<br> +<br> +#endif<br> diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c<br> index 17fe867aeb..5656c654e1 100644<br> --- a/accel/tcg/user-exec.c<br> +++ b/accel/tcg/user-exec.c<br> @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,<br> return size ? g2h(env_cpu(env), addr) : NULL;<br> }<br> <br> -#if defined(__arm__)<br> -<br> -#if defined(__NetBSD__)<br> -#include <ucontext.h><br> -#include <sys/siginfo.h><br> -#endif<br> -<br> -int cpu_signal_handler(int host_signum, void *pinfo,<br> - void *puc)<br> -{<br> - siginfo_t *info = pinfo;<br> -#if defined(__NetBSD__)<br> - ucontext_t *uc = puc;<br> - siginfo_t *si = pinfo;<br> -#else<br> - ucontext_t *uc = puc;<br> -#endif<br> - unsigned long pc;<br> - uint32_t fsr;<br> - int is_write;<br> -<br> -#if defined(__NetBSD__)<br> - pc = uc->uc_mcontext.__gregs[_REG_R15];<br> -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))<br> - pc = uc->uc_mcontext.gregs[R15];<br> -#else<br> - pc = uc->uc_mcontext.arm_pc;<br> -#endif<br> -<br> -#ifdef __NetBSD__<br> - fsr = si->si_trap;<br> -#else<br> - fsr = uc->uc_mcontext.error_code;<br> -#endif<br> - /*<br> - * In the FSR, bit 11 is WnR, assuming a v6 or<br> - * later processor. On v5 we will always report<br> - * this as a read, which will fail later.<br> - */<br> - is_write = extract32(fsr, 11, 1);<br> - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);<br> -}<br> -<br> -#elif defined(__aarch64__)<br> +#if defined(__aarch64__)<br> <br> #if defined(__NetBSD__)<br> <br> -- <br> 2.25.1<br> <br> </blockquote></div></div>
diff --git a/linux-user/host/arm/host-signal.h b/linux-user/host/arm/host-signal.h index f4b4d65031..6932224c1c 100644 --- a/linux-user/host/arm/host-signal.h +++ b/linux-user/host/arm/host-signal.h @@ -1 +1,29 @@ -#define HOST_SIGNAL_PLACEHOLDER +/* + * host-signal.h: signal info dependent on the host architecture + * + * Copyright (C) 2021 Linaro Limited + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef ARM_HOST_SIGNAL_H +#define ARM_HOST_SIGNAL_H + +static inline uintptr_t host_signal_pc(ucontext_t *uc) +{ + return uc->uc_mcontext.arm_pc; +} + +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) +{ + /* + * In the FSR, bit 11 is WnR, assuming a v6 or + * later processor. On v5 we will always report + * this as a read, which will fail later. + */ + uint32_t fsr = uc->uc_mcontext.error_code; + return extract32(fsr, 11, 1); +} + +#endif diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 17fe867aeb..5656c654e1 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -255,50 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong addr, int size, return size ? g2h(env_cpu(env), addr) : NULL; } -#if defined(__arm__) - -#if defined(__NetBSD__) -#include <ucontext.h> -#include <sys/siginfo.h> -#endif - -int cpu_signal_handler(int host_signum, void *pinfo, - void *puc) -{ - siginfo_t *info = pinfo; -#if defined(__NetBSD__) - ucontext_t *uc = puc; - siginfo_t *si = pinfo; -#else - ucontext_t *uc = puc; -#endif - unsigned long pc; - uint32_t fsr; - int is_write; - -#if defined(__NetBSD__) - pc = uc->uc_mcontext.__gregs[_REG_R15]; -#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3)) - pc = uc->uc_mcontext.gregs[R15]; -#else - pc = uc->uc_mcontext.arm_pc; -#endif - -#ifdef __NetBSD__ - fsr = si->si_trap; -#else - fsr = uc->uc_mcontext.error_code; -#endif - /* - * In the FSR, bit 11 is WnR, assuming a v6 or - * later processor. On v5 we will always report - * this as a read, which will fail later. - */ - is_write = extract32(fsr, 11, 1); - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); -} - -#elif defined(__aarch64__) +#if defined(__aarch64__) #if defined(__NetBSD__)