From patchwork Fri Apr 22 10:04:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 564795 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp344753map; Fri, 22 Apr 2022 03:38:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwyb66gbR56KXRQlUGaP+Uw0Sr3o2n02Lb3SyWlAe6QUgPqgCPqMZpFexMe5FL/poe6PkiM X-Received: by 2002:a05:622a:5c7:b0:2e1:d599:9e0d with SMTP id d7-20020a05622a05c700b002e1d5999e0dmr2560254qtb.491.1650623879946; Fri, 22 Apr 2022 03:37:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650623879; cv=none; d=google.com; s=arc-20160816; b=ulwOxkhGHqhIviEKEoel5nWT2k7m+Pz0Ujles5aC2acBb7LlFE2fPjVEQS4rYxafCP ExxBypR5ppaA8m/4t7smqUs/8rMAhtwTaFigUTvuKeqOVo53Q0rRljwj09OPFbM3ESTn 3hDnk5Skkbv7TU1MdyIaO8PGal6QoRtI8clV4wc3t80rXaAuYxGQmW7piNtYTCxw9O4E uo2vTGzd/9GPagM42SQida9He0X6OHUBJ4At4VdhPfK9AtWpybOeZ43Rfi/APGZmec69 iI3Tq0TgHVexJjHo0DHFcNmYOpJOApaaXMBbl38poPO0rymKUl1rt44lW80ZtTSnZyKJ aJ5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dD0gXSrq4cJBnHFPk7NEn42McsBj8OdsQUpLVwThouk=; b=lVZkSyUZ/JgwjIegCfBF+HClUWdYd3waGBYclCsqWbAL51ESPVESLb48sXThKd058N WQwrwXt49q83ZaWLdSt/1T1E0K3AKI9r2suORMxRXVKRN5N0H6xkgoHWKx8M+I21YICu K53bV5jDMnLAAf/P6gIGmQ7eC4G/d/DjZ3K/h53MxrxRjF4T5CNk+yQdtJhL3TNO7V1Q RKZXoqfDIg7aBCZwUk6N5PnNGdQ0ZsfLFVx59l+FnUv5oNTaTNEFiIYcWQKAAwT3JD6R KDHKrcERqnL0OygudIrOUBj7V0fd17OoRtdt7atC4KwzszrD8e9g/IgE1iVHUpq/LQHy 9BvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="QbSVKU/4"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x18-20020ae9e912000000b0069c58379b72si1990619qkf.40.2022.04.22.03.37.59 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Apr 2022 03:37:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="QbSVKU/4"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhqfn-0005Ua-Fx for patch@linaro.org; Fri, 22 Apr 2022 06:37:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhqA6-00052z-Em for qemu-devel@nongnu.org; Fri, 22 Apr 2022 06:05:14 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:43570) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhqA4-0002sM-RJ for qemu-devel@nongnu.org; Fri, 22 Apr 2022 06:05:14 -0400 Received: by mail-wm1-x334.google.com with SMTP id n40-20020a05600c3ba800b0038ff1939b16so5090810wms.2 for ; Fri, 22 Apr 2022 03:05:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dD0gXSrq4cJBnHFPk7NEn42McsBj8OdsQUpLVwThouk=; b=QbSVKU/4WObnW0UWA/uBBMRWjKeeJxeENJOy9OkRDkxrg8I2zZWSeks14ajMpoNWKP HbHEtgGjfkKNsl5PQQKeqXCzPGGtuLxXNYiBEh70b/GQwfXRFTDRylQSa8O3/wfF5VmZ uUK7qdYOaFoXoxCBXtyaOVKDQQE0UryRonII/eZrn6UoH3b/h0apz2eleimS0CmFhpJX Vq96P+Eg0MXLEZ5FqPEHCXvHCn1wLjVM4+6nxNjtrcKCqrD3YftJsnTXy+YkZk9y7KH7 7LR1xRCgXCvf85/C3j3I2hodjPhlXCXoYibbA6e4+5aQSt5ocNY/9aDgotgVuMcT0Qh0 lSCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dD0gXSrq4cJBnHFPk7NEn42McsBj8OdsQUpLVwThouk=; b=bs8MKNO5n0b2ls0Lth05V2C1itLgFgabxRTIKDsjKnfxhfYRYZKiiy+rYFonMyBL16 JSa/zP2QVLVxkrZgF32qmyTl9noAdfd0tlCEIb5ETvUq0HNcfNr9ti6CVLSdiS+KlRLP W/NtryN1DvEve0NTPKMpQPoaVtYDCVJUwqDg3e6yXNt7iZhkFz/cyqjOHL6pW8jzWNbs 6DxmSVUOsXOw2a1vCmCZ6Jf2KeAS3WQ+uuaVSpjm1kyMqMAJgC6DVrOfloQtU1n2EyYT 7bPXd4t1ZOoHXkwN5K20B0bq2TOCC5TahLiITGlSEhPZ3N7I03rFrpcpTBnqSHzHworC oWUw== X-Gm-Message-State: AOAM532c23h0OYt/Mm9Z83v0K4vDzwAV3zjErjapspBfqWZmAhhrnQBG XFZrVSRaPGhtYWa/w5kDGldHoMhbGEIF1g== X-Received: by 2002:a05:600c:4e12:b0:391:18da:1883 with SMTP id b18-20020a05600c4e1200b0039118da1883mr3443054wmq.101.1650621911529; Fri, 22 Apr 2022 03:05:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e16-20020a05600c2dd000b0038ed449cbdbsm4312148wmh.3.2022.04.22.03.05.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 03:05:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity Date: Fri, 22 Apr 2022 11:04:11 +0100 Message-Id: <20220422100432.2288247-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220422100432.2288247-1-peter.maydell@linaro.org> References: <20220422100432.2288247-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In several places in virt.c we calculate the number of redistributors that fit in a region of our memory map, which is the size of the region divided by the size of a single redistributor frame. For GICv4, the redistributor frame is a different size from that for GICv3. Abstract out the calculation of redistributor region capacity so that we have one place we need to change to handle GICv4 rather than several. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220408141550.1271295-41-peter.maydell@linaro.org --- include/hw/arm/virt.h | 9 +++++++-- hw/arm/virt.c | 11 ++++------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 7e76ee26198..360463e6bfb 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -185,11 +185,16 @@ OBJECT_DECLARE_TYPE(VirtMachineState, VirtMachineClass, VIRT_MACHINE) void virt_acpi_setup(VirtMachineState *vms); bool virt_is_acpi_enabled(VirtMachineState *vms); +/* Return number of redistributors that fit in the specified region */ +static uint32_t virt_redist_capacity(VirtMachineState *vms, int region) +{ + return vms->memmap[region].size / GICV3_REDIST_SIZE; +} + /* Return the number of used redistributor regions */ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) { - uint32_t redist0_capacity = - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); assert(vms->gic_version == VIRT_GIC_VERSION_3); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d5f8b0c74ad..1227c64e5b1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -723,8 +723,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) } if (vms->gic_version == VIRT_GIC_VERSION_3) { - uint32_t redist0_capacity = - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST); uint32_t redist0_count = MIN(smp_cpus, redist0_capacity); nb_redist_regions = virt_gicv3_redist_region_count(vms); @@ -743,7 +742,7 @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) if (nb_redist_regions == 2) { uint32_t redist1_capacity = - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); @@ -2048,10 +2047,8 @@ static void machvirt_init(MachineState *machine) * many redistributors we can fit into the memory map. */ if (vms->gic_version == VIRT_GIC_VERSION_3) { - virt_max_cpus = - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; - virt_max_cpus += - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; + virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST) + + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); } else { virt_max_cpus = GIC_NCPU; }