From patchwork Thu Apr 28 14:39:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 567177 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp5547618map; Thu, 28 Apr 2022 08:10:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx2JwhMtfphDBwGWvjNMaRvZ0fkI6ox6ceQ2UUSQbwFhK/6lr8AByW7sO48tSnLB2VWCXrP X-Received: by 2002:a05:6602:2f01:b0:5ec:f99a:93a1 with SMTP id q1-20020a0566022f0100b005ecf99a93a1mr14212910iow.109.1651158633497; Thu, 28 Apr 2022 08:10:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651158633; cv=none; d=google.com; s=arc-20160816; b=ZIJfh7bqmUeOFKM2RdAA1OOKDY4kQZMVwVLzWrV8Ukw6D8Kzt/mS3T9RBhT3PMCdwZ Dya6J/ZxdCCnj/qnSPLUTLNXH4SFpjtFxj3PPlcInyZ3PZrl7jJeZWAM2Pf+lSW4CKI3 8qPifMfIE7DHx+WXeeC06L03vTLoDUb7j8JiMWggxZLwyI3UHVPI0DTGlfX76TZEacaS J96HPNLbHOyvTZJredIMPXJnYYv/koAM7g4DeosPwiJt4ia850lsOuF2n2BwWiXWMuRt rEJ4Ki6Ovh65HqqWLbrltgPrg4+MHAtmLDPaFL22TznM2KB+Ccc4rdI+5REB2meSJmiV zaSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=zcbQ/6t+eYvR1xX9UosyZUxzrXgkRoMDs+Bnhnu9fZU=; b=lelx96K64Cwqy402Z8+xNKovAZZm7NYrXoswCw08uvv0HgJ76Ehh11hIkFNS6m8Gvm yoyBUR5koQmd+WyfenMOMbagpovgsOH7c1sFKih0YV8+slnRc8mdBu0dMaCqwREOn1Eo dO7u5OPFKHI0nawSIypIj7YZiiGUpD1dNwEG6BLDOl83XAI8l9ZZhnpPUWCh0GyQwvY9 PdXxcvy8alCm3lgJ81pJwOwHVXmJqxUQ8Lik8M6VnciGXi0tFUEK8eBEfKoRxYm33vBB wNeS+8dmMnaO4v9cC9qQJiqwBYZUOLQagJwl3g6JJJKilSW0RjXrKBvC2sdMWrNlDSJI XJ9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ayPBz7we; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y8-20020a92d208000000b002cda289161asi2075872ily.40.2022.04.28.08.10.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Apr 2022 08:10:33 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ayPBz7we; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nk5mq-0003I6-TP for patch@linaro.org; Thu, 28 Apr 2022 11:10:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nk5K7-0005gi-Tw for qemu-devel@nongnu.org; Thu, 28 Apr 2022 10:40:52 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:55018) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nk5K5-0006Vf-UU for qemu-devel@nongnu.org; Thu, 28 Apr 2022 10:40:51 -0400 Received: by mail-wm1-x335.google.com with SMTP id bg25so3069218wmb.4 for ; Thu, 28 Apr 2022 07:40:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zcbQ/6t+eYvR1xX9UosyZUxzrXgkRoMDs+Bnhnu9fZU=; b=ayPBz7wev04U0gyfsWegJY4IxoNpq8aOXEjEBJsgBXvQH19oM2o5dCs/s+pQU/A0Kd 2uVyXJzc5qyHTIgFvYrgw+6gJn50Lxt59pzjY/57cb+CV43HrGgV8BDXGZRWiFmJhKRC gaFCjea9Afe01Mwm+5jbFxovkRsB6fkx4c2gk/N7D4ZQI32glZz7BtknUflDeEzGVZfy CVHCuD/NC5YCIHCrZ1SMdLAtugYhfcLqq8KaT0VR1M+9ZA6gzshUC8L1fvKXjhBxDscc B6ZhjZtimaRBRYolcoKypT8BkP8kddhkHjy6k9NtjebFV/4GEGrdna9EDiLy4fRYlM1Q oP3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zcbQ/6t+eYvR1xX9UosyZUxzrXgkRoMDs+Bnhnu9fZU=; b=AV2gJNa4NKwoOl1q5vj9i3CxJjpCptjyjQnMEx/cOWdNsalFpRkVENDPBGdD26mWVT FHQw4stdfxiHMXHULMod7dELns/FICkzj97FNtwsAHo/AYfz3sw4pPal4WXDBJH528Fr LJaCeFLnhkLmI5jv7JkdYqduh1cbEBG2hTjPzfVBCpfa4FZW2trnoWyj8V3HT3NlxodM +azu5FeYLxfTpUqS4Rl3IGYSFXwtm5OGk6GWUVhY2x3zfzXYacID7vx3lPKqTLvUHopn thdNAw4P453fhSHMPM6B1EIbDWHaxztHFZOo7do4D1Syv3FDIVCQRPxHRofuW1LBb8/p dMWw== X-Gm-Message-State: AOAM533f3J6ncrYS0TQQPQ9m/jWO/29XU9b+VSIJU2PxApzUkDspEUXs D86xUQi1MRDsy14vHBfH5floDWUFRan8mw== X-Received: by 2002:a7b:c7c2:0:b0:394:18b:4220 with SMTP id z2-20020a7bc7c2000000b00394018b4220mr8225812wmk.118.1651156848209; Thu, 28 Apr 2022 07:40:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bh26-20020a05600c3d1a00b003928db85759sm130221wmb.15.2022.04.28.07.40.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 07:40:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/54] hw/arm/smmuv3: Cache event fault record Date: Thu, 28 Apr 2022 15:39:54 +0100 Message-Id: <20220428143958.2451229-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428143958.2451229-1-peter.maydell@linaro.org> References: <20220428143958.2451229-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Jean-Philippe Brucker The Record bit in the Context Descriptor tells the SMMU to report fault events to the event queue. Since we don't cache the Record bit at the moment, access faults from a cached Context Descriptor are never reported. Store the Record bit in the cached SMMUTransCfg. Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback") Signed-off-by: Jean-Philippe Brucker Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-id: 20220427111543.124620-1-jean-philippe@linaro.org Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 - include/hw/arm/smmu-common.h | 1 + hw/arm/smmuv3.c | 14 +++++++------- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index d1885ae3f25..6de52bbf4da 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -387,7 +387,6 @@ typedef struct SMMUEventInfo { SMMUEventType type; uint32_t sid; bool recorded; - bool record_trans_faults; bool inval_ste_allowed; union { struct { diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h index 706be3c6d0a..21e62342e92 100644 --- a/include/hw/arm/smmu-common.h +++ b/include/hw/arm/smmu-common.h @@ -71,6 +71,7 @@ typedef struct SMMUTransCfg { bool disabled; /* smmu is disabled */ bool bypassed; /* translation is bypassed */ bool aborted; /* translation is aborted */ + bool record_faults; /* record fault events */ uint64_t ttb; /* TT base address */ uint8_t oas; /* output address width */ uint8_t tbi; /* Top Byte Ignore */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 707eb430c23..8b1d8103dc8 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -527,7 +527,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had); } - event->record_trans_faults = CD_R(cd); + cfg->record_faults = CD_R(cd); return 0; @@ -680,7 +680,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, tt = select_tt(cfg, addr); if (!tt) { - if (event.record_trans_faults) { + if (cfg->record_faults) { event.type = SMMU_EVT_F_TRANSLATION; event.u.f_translation.addr = addr; event.u.f_translation.rnw = flag & 0x1; @@ -696,7 +696,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, if (cached_entry) { if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { status = SMMU_TRANS_ERROR; - if (event.record_trans_faults) { + if (cfg->record_faults) { event.type = SMMU_EVT_F_PERMISSION; event.u.f_permission.addr = addr; event.u.f_permission.rnw = flag & 0x1; @@ -720,28 +720,28 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, event.u.f_walk_eabt.addr2 = ptw_info.addr; break; case SMMU_PTW_ERR_TRANSLATION: - if (event.record_trans_faults) { + if (cfg->record_faults) { event.type = SMMU_EVT_F_TRANSLATION; event.u.f_translation.addr = addr; event.u.f_translation.rnw = flag & 0x1; } break; case SMMU_PTW_ERR_ADDR_SIZE: - if (event.record_trans_faults) { + if (cfg->record_faults) { event.type = SMMU_EVT_F_ADDR_SIZE; event.u.f_addr_size.addr = addr; event.u.f_addr_size.rnw = flag & 0x1; } break; case SMMU_PTW_ERR_ACCESS: - if (event.record_trans_faults) { + if (cfg->record_faults) { event.type = SMMU_EVT_F_ACCESS; event.u.f_access.addr = addr; event.u.f_access.rnw = flag & 0x1; } break; case SMMU_PTW_ERR_PERMISSION: - if (event.record_trans_faults) { + if (cfg->record_faults) { event.type = SMMU_EVT_F_PERMISSION; event.u.f_permission.addr = addr; event.u.f_permission.rnw = flag & 0x1;