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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id j10-20020a62b60a000000b0050dc762817dsm1753826pff.87.2022.04.30.10.02.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:02:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/m68k: Clear mach in m68k_cpu_disas_set_info Date: Sat, 30 Apr 2022 10:02:24 -0700 Message-Id: <20220430170225.326447-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430170225.326447-1-richard.henderson@linaro.org> References: <20220430170225.326447-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Zero selects all cpu features in disas/m68k.c, which is really what we want -- not limited to 68040. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- target/m68k/cpu.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c7aeb7da9c..5671067923 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -75,12 +75,8 @@ static void m68k_cpu_reset(DeviceState *dev) static void m68k_cpu_disas_set_info(CPUState *s, disassemble_info *info) { - M68kCPU *cpu = M68K_CPU(s); - CPUM68KState *env = &cpu->env; info->print_insn = print_insn_m68k; - if (m68k_feature(env, M68K_FEATURE_M68000)) { - info->mach = bfd_mach_m68040; - } + info->mach = 0; } /* CPU models */