From patchwork Mon May 9 11:58:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 570970 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:66c4:0:0:0:0 with SMTP id x4csp3929140mal; Mon, 9 May 2022 05:06:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJztmpxDZ7GJmO8pZf0a+xNT86KPJrq6928614lxiQJvNfS5Pj+6dsn+lHGjASS8pcgWIOQr X-Received: by 2002:a05:622a:15c5:b0:2f3:c195:8d5 with SMTP id d5-20020a05622a15c500b002f3c19508d5mr14667037qty.369.1652098013351; Mon, 09 May 2022 05:06:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1652098013; cv=none; d=google.com; s=arc-20160816; b=nmmn+q1Vn/dXVnoPbEwMHJlR+t/E1PLnVHDa8kh3CnZCgEBdGhpQTv0zFbUeXjrfC+ soVpcnO6lVsNxVXkkFAv+QvG7r+h5mwLSWLJXtrgmAm3Goka/GuKaP4u5sVpu+E7EbRf /+AOZOGiGpzuLeygUS69Ai+b+lRzrELXjFsKlcCCESqi39l5wetbKwG385w0mxHZZOPF TnttOnlIMeQje8aE0lQVoYWzwGoNj5SqV8V9itNdyZrdNLveIgwUPpzipjUqeSFjHG4A u6zTWZNbOmCnJt9ysm1kWO46wJbE1m4TySaSOxCJroe2iE/S/7uhoKTJG+Ry/Z1rJl+i 7ZSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qa9bXLZrtUjkR08O1nmZU1gZrJzLSKj+bcC5vCf6akQ=; b=wrcD4DbhD8Stj3Q2J2ucQWt6QXRy+wlYSiJyqOtIl3bvIhIziFuSA6Cz05rStr0Su1 r+cxlGMf99TFf5eg4WxEoW2dLfeMAVwzHwReZJGutk2IKGM+aGszfNMwqVWD2FcU68rW DOhT5V8XxmYKQeZxT+tWarvSXhrXhoWbspBBXgfKI3X1Amh9d2zFTJDRWISKWBF0Hbyp PB1M/a9gFylGkSrUmagJcESkwXWKCmostEDoYU9fXczo6jbTPXzuY7p3kTgFArJp+Ouq tmFXMUZBcEBcCBR99V/K8GqRXwW6DLd9TfLhqi2TGKBQHwEIgjnmCpgjPvVhuby4aHh2 l4hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lBg71FUe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s31-20020a05622a1a9f00b002f12dadaa45si7719591qtc.612.2022.05.09.05.06.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 May 2022 05:06:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lBg71FUe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:58316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2A8-00074g-UZ for patch@linaro.org; Mon, 09 May 2022 08:06:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22Y-0007GU-Dx for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:02 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:45640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22W-0001IW-L9 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:02 -0400 Received: by mail-wr1-x42a.google.com with SMTP id w4so19070775wrg.12 for ; Mon, 09 May 2022 04:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qa9bXLZrtUjkR08O1nmZU1gZrJzLSKj+bcC5vCf6akQ=; b=lBg71FUejsMOGgDjkg2a3q3HoFPcoiTPkAk35Re3AJwRs0yh+f/bK5BJdJjBXlC8hs OosnlXDx+F65FS74EZDPU15JKWM6kBHI5LMcvUoRnUlJay8BC68KNDSkpZu0iKhMg46G QPA8NDchVgqlkltUAz76bGCJ9ABiFZXg7A4XrWsO2ljNNBncz901Rr12lYntwSI+qVx8 V/mdTqt0SFA7xCnBUsk1AV0z9AvDa+EqFchN1s3utb5XqjKwLg80DAHrul19XvhAE7Gb p1eD9/KwQ+neTnAGQQKindJ/XkXgBEAgXAVD22liBy9X3gSSSX0r5fSB0OiD8R+Cc4RG 5uUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qa9bXLZrtUjkR08O1nmZU1gZrJzLSKj+bcC5vCf6akQ=; b=imhEB6L4dBCIaUqU7/GUp8xo4tVKWP2EZNzngb4JfM5/ds8m41wuA94GEZO5fK6qQO 3lxZoA42aTt5Qxr/dK6Db5EuVp49RgTJzZFy9eU+9yURTAe2TUlVY6WnVx0IcsdNWRI6 +Xwemqi7G7kyJNzszVtVgxWvsBrwQ/I3qouFmILbuzOnFB/Qeiz4jJehlp6YP46Ut89m d43iyAQF+9qgisZ0JSGe0UWtpW76x/4mmQ1PQGom4kfq4OLn/ohB6ryTDOjcUPMN4JGU nNUth/aHPv/Mfo0j1fmasKcoArgavPWD6bw4El5SA4LlciY2b/iJXNJWfJguhiqqBELU oWmg== X-Gm-Message-State: AOAM530cl0lU5ZZ6ZVRS59NleRDQPjwJisK7AJucDQ0TcEO2VHd7T05q ZrzVj+OFTKwYOVUvTtBgU9aVfS11KkLtuQ== X-Received: by 2002:a05:6000:2a5:b0:20c:520a:a12e with SMTP id l5-20020a05600002a500b0020c520aa12emr13088558wry.629.1652097539234; Mon, 09 May 2022 04:58:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Mon, 9 May 2022 12:58:27 +0100 Message-Id: <20220509115848.3521805-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01176b2569f..7995ff27126 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1801,11 +1801,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) */ unset_feature(env, ARM_FEATURE_EL3); - /* Disable the security extension feature bits in the processor feature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &= ~0xf0; - cpu->isar.id_aa64pfr0 &= ~0xf000; + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0); + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } if (!cpu->has_el2) { @@ -1836,12 +1838,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) } if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &= ~0xf00; - cpu->isar.id_pfr1 &= ~0xf000; + cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } #ifndef CONFIG_USER_ONLY