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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Date: Mon, 9 May 2022 12:58:24 +0100 Message-Id: <20220509115848.3521805-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu_tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index f9094c17525..9aa2f737c1e 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1084,6 +1084,10 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, ID_PFR2, SSBS, 1); cpu->isar.id_pfr2 = t; + t = cpu->isar.id_dfr0; + t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 = t; + #ifdef CONFIG_USER_ONLY /* * Break with true ARMv8 and add back old-style VFP short-vector support.