From patchwork Tue Jun 21 20:46:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 583622 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5036:0:0:0:0 with SMTP id e22csp2045229mab; Tue, 21 Jun 2022 13:54:46 -0700 (PDT) X-Google-Smtp-Source: AGRyM1uTIEXKBvAynv1TeIelvw+0efJm5OQsaZyu7NX/o74KfPKP0nStnpN1ltAc7UE+yITzN8kU X-Received: by 2002:a0c:e6a2:0:b0:470:45c8:6a84 with SMTP id j2-20020a0ce6a2000000b0047045c86a84mr9170933qvn.38.1655844886374; Tue, 21 Jun 2022 13:54:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1655844886; cv=none; d=google.com; s=arc-20160816; b=zX1gEzCaiJPpkCYRAJQlYBlEn8Jf8S3n0rcpxZFgthmNJyhBQRA271Fvq3YTMxDErG gvvWDbUmxV/JLHPoSYysmma1UUrrR+hFVtyMv1WW53QnWBOwzfWbRyMvrsf+YTn/fumg /xIhvtFq3wHlZimMHl/FI3UrnpwpWKOepKyWiz2apAoA1DpZM5wMTEqo942C1Wh55DAf K+aQCWkvadf9vxQ8Ph4S24DjHRO8KDBEZCVDDgCJMDaJpf/WikFAKZHxmuW2hQ3GPhOQ 5hf+3mi7CNwbeqhTJJSynXPUe91XXSMe0JmffPx9w4Q3G5VhNWlSXezEqtHmGPJ+6dHR 401w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=h3YLx19yslSTTaLGcQTbBkJC0TNZDbNOKWylq2WnPkw=; b=GCJ2rzR5JsFVoJgFEnrbpTu7gdp3rlEZbyFA041GyR8nvJYXk3mF1kwWwZmJ23oQe0 Vvv8Q6RY8YuYfmxAzOhV5Mlk2ujZOqpuw6ssxVjcNeGclrvqwB3qAFGXwBjha9xt/CA7 TX1iLoyPloFcjBAf4vqTIjrlmOhDa0FIFrM9okWC1nQIPxa5if3UCaG+sLs85H8o5sKi lMhbSknfBj8qPsMCq5m1aRUn6Ek52vUrME6iaPm+SLPGS4Lnja2kLDjgaMLxA4gqGj4A 5jVC2Cd2Qvt3x1/hMMt21MKOTCJ/6YHObJugyDS9cTD56U6FRIVIe6pY3h9SbhRaFkjY Xj8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wXRAJgeu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y12-20020a05622a120c00b002f91696bb92si9398352qtx.705.2022.06.21.13.54.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 21 Jun 2022 13:54:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wXRAJgeu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1o3ktZ-000855-VU for patch@linaro.org; Tue, 21 Jun 2022 16:54:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1o3km2-0006dj-W8 for qemu-devel@nongnu.org; Tue, 21 Jun 2022 16:47:01 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:41911) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1o3kly-00016r-GU for qemu-devel@nongnu.org; Tue, 21 Jun 2022 16:46:58 -0400 Received: by mail-pf1-x432.google.com with SMTP id i64so14160581pfc.8 for ; Tue, 21 Jun 2022 13:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h3YLx19yslSTTaLGcQTbBkJC0TNZDbNOKWylq2WnPkw=; b=wXRAJgeu88VAK0d4jbnRHsKr/e7hSkdPgzlcz+QpmuqS3cVaooJ6wm/+BVotY672p+ 80WHm1MqqCa9zvwk9gRaKKsK9yK1R5IrolEeLuFXBQAUUmJgzgdRuGbhuENnRe9srWTF EcJ4/V2jJYwLkH/Z4J1oL6KfnnaPy0tP8AjZkbbMP3M0lgQGjZ0KCDQJFdm7fkfsKNUn gAx158K3//zxJe1xJ8MO1yEAI6tTlzBtiBHG/7P3fakZcDssy0qJHd/xtnhXoEKpUZ8k msjJfq71ufwwyDG+e81YG0qW2+r4Edgp5KOfE+vp5tXo2Sum2QdR26VtLCwcuDXLY0iv 3mfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h3YLx19yslSTTaLGcQTbBkJC0TNZDbNOKWylq2WnPkw=; b=cX547mwzw2D9UzfYtIidO32h1ZylcVWDcL4hGsB+V7k4kPG9QNSgO+XAr3xMadGLLN fx6uzQ4rCQISXj6ukUrxd7WUSPoibcSODZa6IDY2ad1/2CbXRhCyno3gg1KlNq7uYCdt SHu3Pw+DLbrOXJwSNcHiqPWgwbth6IN28V0VSOaFxceLq3zybA9kH4lYtlOp2W3A+MZq LjJzIeJVCmdxtSMdDWvpyx++Z/uvlsucSiHfHexaHsPPMB+/XO23FBVPG724h28Pj0Wa +cpGzfKJCfpWDpxmGAU4WRbxB8uC5pnTyOgYcOocg6bCW2uV8h7tlDWON71wQi2qvYIu 8yIw== X-Gm-Message-State: AJIora/QpmM2dYuI4RWY6LEapxe+UMzLFJUrRu/ERys9rV+wwoWK0PKx tBpdi5pbqYB2bkqu00R1FXfT3hOfisCCRg== X-Received: by 2002:a63:4b02:0:b0:3fc:a31a:304 with SMTP id y2-20020a634b02000000b003fca31a0304mr27235325pga.121.1655844413118; Tue, 21 Jun 2022 13:46:53 -0700 (PDT) Received: from stoup.. ([2602:47:d49e:3c01:8adc:a144:6ec2:4d71]) by smtp.gmail.com with ESMTPSA id p66-20020a625b45000000b005252defb016sm3649674pfb.122.2022.06.21.13.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 13:46:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Nicholas Piggin , Peter Maydell Subject: [PULL 9/9] util/cacheflush: Optimize flushing when ppc host has coherent icache Date: Tue, 21 Jun 2022 13:46:43 -0700 Message-Id: <20220621204643.371397-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220621204643.371397-1-richard.henderson@linaro.org> References: <20220621204643.371397-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Nicholas Piggin On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates that we can use a simplified 3 instruction flush sequence. Signed-off-by: Nicholas Piggin Message-Id: <20220519141131.29839-1-npiggin@gmail.com> [rth: update after merging cacheflush.c and cacheinfo.c] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org> --- util/cacheflush.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/util/cacheflush.c b/util/cacheflush.c index 01b6cb7583..2c2c73e085 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -117,6 +117,10 @@ static void sys_cache_info(int *isize, int *dsize) * Architecture (+ OS) specific cache detection mechanisms. */ +#if defined(__powerpc__) +static bool have_coherent_icache; +#endif + #if defined(__aarch64__) && !defined(CONFIG_DARWIN) /* Apple does not expose CTR_EL0, so we must use system interfaces. */ static uint64_t save_ctr_el0; @@ -156,6 +160,7 @@ static void arch_cache_info(int *isize, int *dsize) if (*dsize == 0) { *dsize = qemu_getauxval(AT_DCACHEBSIZE); } + have_coherent_icache = qemu_getauxval(AT_HWCAP) & PPC_FEATURE_ICACHE_SNOOP; } #else @@ -298,8 +303,24 @@ void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len) { uintptr_t p, b, e; - size_t dsize = qemu_dcache_linesize; - size_t isize = qemu_icache_linesize; + size_t dsize, isize; + + /* + * Some processors have coherent caches and support a simplified + * flushing procedure. See + * POWER9 UM, 4.6.2.2 Instruction Cache Block Invalidate (icbi) + * https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k + */ + if (have_coherent_icache) { + asm volatile ("sync\n\t" + "icbi 0,%0\n\t" + "isync" + : : "r"(rx) : "memory"); + return; + } + + dsize = qemu_dcache_linesize; + isize = qemu_icache_linesize; b = rw & ~(dsize - 1); e = (rw + len + dsize - 1) & ~(dsize - 1);