@@ -17,6 +17,7 @@
#include "hw/char/bcm2835_aux.h"
#include "hw/display/bcm2835_fb.h"
#include "hw/dma/bcm2835_dma.h"
+#include "hw/or-irq.h"
#include "hw/intc/bcm2835_ic.h"
#include "hw/misc/bcm2835_property.h"
#include "hw/misc/bcm2835_rng.h"
@@ -55,6 +56,7 @@ struct BCM2835PeripheralState {
BCM2835AuxState aux;
BCM2835FBState fb;
BCM2835DMAState dma;
+ qemu_or_irq orgated_dma_irq;
BCM2835ICState ic;
BCM2835PropertyState property;
BCM2835RngState rng;
@@ -23,6 +23,13 @@
/* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
#define BCM2835_SDHC_CAPAREG 0x52134b4
+/*
+ * According to Linux driver & DTS, dma channels 0--10 have separate IRQ,
+ * while channels 11--14 share one IRQ:
+ */
+#define SEPARATE_DMA_IRQ_MAX 10
+#define ORGATED_DMA_IRQ_COUNT 4
+
static void create_unimp(BCM2835PeripheralState *ps,
UnimplementedDeviceState *uds,
const char *name, hwaddr ofs, hwaddr size)
@@ -101,6 +108,11 @@ static void bcm2835_peripherals_init(Object *obj)
/* DMA Channels */
object_initialize_child(obj, "dma", &s->dma, TYPE_BCM2835_DMA);
+ object_initialize_child(obj, "orgated-dma-irq",
+ &s->orgated_dma_irq, TYPE_OR_IRQ);
+ object_property_set_int(OBJECT(&s->orgated_dma_irq), "num-lines",
+ ORGATED_DMA_IRQ_COUNT, &error_abort);
+
object_property_add_const_link(OBJECT(&s->dma), "dma-mr",
OBJECT(&s->gpu_bus_mr));
@@ -322,12 +334,24 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
memory_region_add_subregion(&s->peri_mr, DMA15_OFFSET,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dma), 1));
- for (n = 0; n <= 12; n++) {
+ for (n = 0; n <= SEPARATE_DMA_IRQ_MAX; n++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), n,
qdev_get_gpio_in_named(DEVICE(&s->ic),
BCM2835_IC_GPU_IRQ,
INTERRUPT_DMA0 + n));
}
+ if (!qdev_realize(DEVICE(&s->orgated_dma_irq), NULL, errp)) {
+ return;
+ }
+ for (n = 0; n < ORGATED_DMA_IRQ_COUNT; n++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma),
+ SEPARATE_DMA_IRQ_MAX + 1 + n,
+ qdev_get_gpio_in(DEVICE(&s->orgated_dma_irq), n));
+ }
+ qdev_connect_gpio_out(DEVICE(&s->orgated_dma_irq), 0,
+ qdev_get_gpio_in_named(DEVICE(&s->ic),
+ BCM2835_IC_GPU_IRQ,
+ INTERRUPT_DMA0 + SEPARATE_DMA_IRQ_MAX + 1));
/* THERMAL */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->thermal), errp)) {
new file mode 100644
@@ -0,0 +1,118 @@
+/*
+ * QTest testcase for BCM283x DMA engine (on Raspberry Pi 3)
+ * and its interrupts coming to Interrupt Controller.
+ *
+ * Copyright (c) 2022 Auriga LLC
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest-single.h"
+
+/* Offsets in raspi3b platform: */
+#define RASPI3_DMA_BASE 0x3f007000
+#define RASPI3_IC_BASE 0x3f00b200
+
+/* Used register/fields definitions */
+
+/* DMA engine registers: */
+#define BCM2708_DMA_CS 0
+#define BCM2708_DMA_ACTIVE (1 << 0)
+#define BCM2708_DMA_INT (1 << 2)
+
+#define BCM2708_DMA_ADDR 0x04
+
+#define BCM2708_DMA_INT_STATUS 0xfe0
+
+/* DMA Trasfer Info fields: */
+#define BCM2708_DMA_INT_EN (1 << 0)
+#define BCM2708_DMA_D_INC (1 << 4)
+#define BCM2708_DMA_S_INC (1 << 8)
+
+/* Interrupt controller registers: */
+#define IRQ_PENDING_BASIC 0x00
+#define IRQ_GPU_PENDING1_AGGR (1 << 8)
+#define IRQ_PENDING_1 0x04
+#define IRQ_ENABLE_1 0x10
+
+/* Data for the test: */
+#define SCB_ADDR 256
+#define S_ADDR 32
+#define D_ADDR 64
+#define TXFR_LEN 32
+const uint32_t check_data = 0x12345678;
+
+static void bcm2835_dma_test_interrupt(int dma_c, int irq_line)
+{
+ uint64_t dma_base = RASPI3_DMA_BASE + dma_c * 0x100;
+ int gpu_irq_line = 16 + irq_line;
+
+ /* Check that interrupts are silent by default: */
+ writel(RASPI3_IC_BASE + IRQ_ENABLE_1, 1 << gpu_irq_line);
+ int isr = readl(dma_base + BCM2708_DMA_INT_STATUS);
+ g_assert_cmpint(isr, ==, 0);
+ uint32_t reg0 = readl(dma_base + BCM2708_DMA_CS);
+ g_assert_cmpint(reg0, ==, 0);
+ uint32_t ic_pending = readl(RASPI3_IC_BASE + IRQ_PENDING_BASIC);
+ g_assert_cmpint(ic_pending, ==, 0);
+ uint32_t gpu_pending1 = readl(RASPI3_IC_BASE + IRQ_PENDING_1);
+ g_assert_cmpint(gpu_pending1, ==, 0);
+
+ /* Prepare Control Block: */
+ writel(SCB_ADDR + 0, BCM2708_DMA_S_INC | BCM2708_DMA_D_INC |
+ BCM2708_DMA_INT_EN); /* transfer info */
+ writel(SCB_ADDR + 4, S_ADDR); /* source address */
+ writel(SCB_ADDR + 8, D_ADDR); /* destination address */
+ writel(SCB_ADDR + 12, TXFR_LEN); /* transfer length */
+ writel(dma_base + BCM2708_DMA_ADDR, SCB_ADDR);
+
+ writel(S_ADDR, check_data);
+ for (int word = S_ADDR + 4; word < S_ADDR + TXFR_LEN; word += 4) {
+ writel(word, ~check_data);
+ }
+ /* Perform the transfer: */
+ writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_ACTIVE);
+
+ /* Check that destination == source: */
+ uint32_t data = readl(D_ADDR);
+ g_assert_cmpint(data, ==, check_data);
+ for (int word = D_ADDR + 4; word < D_ADDR + TXFR_LEN; word += 4) {
+ data = readl(word);
+ g_assert_cmpint(data, ==, ~check_data);
+ }
+
+ /* Check that interrupt status is set both in DMA and IC controllers: */
+ isr = readl(RASPI3_DMA_BASE + BCM2708_DMA_INT_STATUS);
+ g_assert_cmpint(isr, ==, 1 << dma_c);
+
+ ic_pending = readl(RASPI3_IC_BASE + IRQ_PENDING_BASIC);
+ g_assert_cmpint(ic_pending, ==, IRQ_GPU_PENDING1_AGGR);
+
+ gpu_pending1 = readl(RASPI3_IC_BASE + IRQ_PENDING_1);
+ g_assert_cmpint(gpu_pending1, ==, 1 << gpu_irq_line);
+
+ /* Clean up, clear interrupt: */
+ writel(dma_base + BCM2708_DMA_CS, BCM2708_DMA_INT);
+}
+
+static void bcm2835_dma_test_interrupts(void)
+{
+ /* DMA engines 0--10 have separate IRQ lines, 11--14 - only one: */
+ bcm2835_dma_test_interrupt(0, 0);
+ bcm2835_dma_test_interrupt(10, 10);
+ bcm2835_dma_test_interrupt(11, 11);
+ bcm2835_dma_test_interrupt(14, 11);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+ g_test_init(&argc, &argv, NULL);
+ qtest_add_func("/bcm2835/dma/test_interrupts",
+ bcm2835_dma_test_interrupts);
+ qtest_start("-machine raspi3b");
+ ret = g_test_run();
+ qtest_end();
+ return ret;
+}
@@ -218,7 +218,8 @@ qtests_aarch64 = \
['arm-cpu-features',
'numa-test',
'boot-serial-test',
- 'migration-test']
+ 'migration-test',
+ 'bcm2835-dma-test']
qtests_s390x = \
(slirp.found() ? ['pxe-test', 'test-netfilter'] : []) + \