| Message ID | 20220822152741.1617527-35-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Implement FEAT_HAFDBS | expand |
On Mon, 22 Aug 2022 at 17:50, Richard Henderson <richard.henderson@linaro.org> wrote: > > Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so > that we use is_state instead of the currend security state. "is_secure", "current" > These AT* operations have been broken since arm_hcr_el2_eff > gained a check for "el2 enabled" for Secure EL2. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/ptw.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/arm/ptw.c b/target/arm/ptw.c > index fe06bb032b..4da932b464 100644 > --- a/target/arm/ptw.c > +++ b/target/arm/ptw.c > @@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, > } > } > > - hcr_el2 = arm_hcr_el2_eff(env); > + hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure); > > switch (mmu_idx) { > case ARMMMUIdx_Stage2: > @@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, > return ~0; > } > > - hcr = arm_hcr_el2_eff(env); > + hcr = arm_hcr_el2_eff_secstate(env, is_secure); > if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { > /* > * PTW set and S1 walk touched S2 Device memory: > @@ -2360,7 +2360,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, > } > > /* Combine the S1 and S2 cache attributes. */ > - hcr = arm_hcr_el2_eff(env); > + hcr = arm_hcr_el2_eff_secstate(env, is_secure); > if (hcr & HCR_DC) { > /* > * HCR.DC forces the first stage attributes to > @@ -2493,7 +2493,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, > result->page_size = TARGET_PAGE_SIZE; > > /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ > - hcr = arm_hcr_el2_eff(env); > + hcr = arm_hcr_el2_eff_secstate(env, is_secure); > result->cacheattrs.shareability = 0; > result->cacheattrs.is_s2_format = false; > if (hcr & HCR_DC) { > -- > 2.34.1 Otherwise Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fe06bb032b..4da932b464 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, } } - hcr_el2 = arm_hcr_el2_eff(env); + hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure); switch (mmu_idx) { case ARMMMUIdx_Stage2: @@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, return ~0; } - hcr = arm_hcr_el2_eff(env); + hcr = arm_hcr_el2_eff_secstate(env, is_secure); if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: @@ -2360,7 +2360,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, } /* Combine the S1 and S2 cache attributes. */ - hcr = arm_hcr_el2_eff(env); + hcr = arm_hcr_el2_eff_secstate(env, is_secure); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to @@ -2493,7 +2493,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, result->page_size = TARGET_PAGE_SIZE; /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr = arm_hcr_el2_eff(env); + hcr = arm_hcr_el2_eff_secstate(env, is_secure); result->cacheattrs.shareability = 0; result->cacheattrs.is_s2_format = false; if (hcr & HCR_DC) {
Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so that we use is_state instead of the currend security state. These AT* operations have been broken since arm_hcr_el2_eff gained a check for "el2 enabled" for Secure EL2. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/ptw.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)