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[209.51.188.17]) by mx.google.com with ESMTPS id gs7-20020a056214226700b0049918d85384si6453545qvb.29.2022.09.06.03.10.07 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Sep 2022 03:10:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eVBQLKgE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:47452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVVWw-0006X1-VN for patch@linaro.org; Tue, 06 Sep 2022 06:10:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45298) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVVSi-00044n-PE for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:05:45 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:39818) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVVSf-00034h-1C for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:05:44 -0400 Received: by mail-wr1-x435.google.com with SMTP id az27so14645079wrb.6 for ; Tue, 06 Sep 2022 03:05:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=zqM+tLT0c4kdL2N5oQ0iibAj5/0Y8nElXOz+WlKsfPg=; b=eVBQLKgEeMHXly4tBYNXHjjpRDjs6M+GyKx7+Fk+TvR8sXcxZiw2jXI33OMuyPexBx bYAWl601XRxFJZFh4SIhrcERSSz+GKFFuWuZMVaRpIm6ql9Q/fdTXK1+d1cIsV4Y5M/7 TtC5VyO9gt+wGfrW5oeNxhUL13PZ1KcQBKC1AYAIWZI1whn6nCEstkCkYdjqo2Cre/ML Eho3zOeGu0PsWp8AmRixCTDT5M915Heb0R5ZQxzevPjMtrEcLsSNtCAk6yJjGiJPjz2L rbItpBFHdHXHasxDAXqmYGQI6xnP8S158a4jUcQM0vqdR7GBQbHSIVoCVQYXDmTTP4KN Wx3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=zqM+tLT0c4kdL2N5oQ0iibAj5/0Y8nElXOz+WlKsfPg=; b=gKF7vBQOhhlBW/1kL6fOxPvXbKLI9N49lnX4U9cKAR6D/3bnaLumR8FBgPxmNBUfDu 05BQp2HAmq/dC+dORM+dsuDNoI4h5rRVgpCXoRJ1BmQBFETNJpv/adRwoUb6lC6ktVLw jkKeHk06/4PwsyojS05SWqX7D1v49+Nw2rTl2VjkazDM80HAPup7NqoaWx0R43v3/AX4 Z7tyx/6Q2jZw+vCdiuzo1RnhafAoz66STXuowNpNEYvrXvFHogAew2VbE4ui6x/hBE4Z vCQpwQbslPjyNLCCXuNsib29ugN6PscGzzq670SJLeeYbQowP2LQUikbeS4m9GmzqYs6 8w1w== X-Gm-Message-State: ACgBeo0il9CPpMPiC2Jxx/hwAC+6C5UGsvCotrnXoRKQjGezubHxA3jW /9rdwMrP7Dh0BuP1ewCmuxWxrTRYMLeivNtY X-Received: by 2002:a5d:6d89:0:b0:228:da8b:2537 with SMTP id l9-20020a5d6d89000000b00228da8b2537mr1022612wrs.585.1662458739131; Tue, 06 Sep 2022 03:05:39 -0700 (PDT) Received: from localhost.localdomain ([2a02:8084:a5c0:5a80:ba98:3a71:8524:e0b1]) by smtp.gmail.com with ESMTPSA id d15-20020a5d6dcf000000b00225307f43fbsm12271081wrz.44.2022.09.06.03.05.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 03:05:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 7/9] target/arm: Introduce gen_pc_plus_diff for aarch64 Date: Tue, 6 Sep 2022 11:05:26 +0100 Message-Id: <20220906100528.343244-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100528.343244-1-richard.henderson@linaro.org> References: <20220906100528.343244-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 41 +++++++++++++++++++++++++++----------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bb744fad3..7dd9b29dbf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -148,9 +148,14 @@ static void reset_btype(DisasContext *s) } } +static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, int diff) +{ + tcg_gen_movi_i64(dest, s->pc_curr + diff); +} + void gen_a64_update_pc(DisasContext *s, int diff) { - tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff); + gen_pc_plus_diff(s, cpu_pc, diff); } /* @@ -1368,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) if (insn & (1U << 31)) { /* BL Branch with link */ - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); } /* B Branch / BL Branch with link */ @@ -2319,11 +2324,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) default: goto do_unallocated; } - gen_a64_set_pc(s, dst); /* BLR also needs to load return address */ if (opc == 1) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; case 8: /* BRAA */ @@ -2346,11 +2357,17 @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) } else { dst = cpu_reg(s, rn); } - gen_a64_set_pc(s, dst); /* BLRAA also needs to load return address */ if (opc == 9) { - tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next); + TCGv_i64 lr = cpu_reg(s, 30); + if (dst == lr) { + TCGv_i64 tmp = new_tmp_a64(s); + tcg_gen_mov_i64(tmp, dst); + dst = tmp; + } + gen_pc_plus_diff(s, lr, curr_insn_len(s)); } + gen_a64_set_pc(s, dst); break; case 4: /* ERET */ @@ -2918,7 +2935,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) tcg_rt = cpu_reg(s, rt); - clean_addr = tcg_constant_i64(s->pc_curr + imm); + clean_addr = new_tmp_a64(s); + gen_pc_plus_diff(s, clean_addr, imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -4262,23 +4280,22 @@ static void disas_ldst(DisasContext *s, uint32_t insn) static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) { unsigned int page, rd; - uint64_t base; - uint64_t offset; + int64_t offset; page = extract32(insn, 31, 1); /* SignExtend(immhi:immlo) -> offset */ offset = sextract64(insn, 5, 19); offset = offset << 2 | extract32(insn, 29, 2); rd = extract32(insn, 0, 5); - base = s->pc_curr; if (page) { /* ADRP (page based) */ - base &= ~0xfff; offset <<= 12; + /* The page offset is ok for TARGET_TB_PCREL. */ + offset -= s->pc_curr & 0xfff; } - tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); + gen_pc_plus_diff(s, cpu_reg(s, rd), offset); } /*