From patchwork Wed Sep 14 16:09:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 605773 Delivered-To: patch@linaro.org Received: by 2002:ab3:1c02:0:b0:1e7:4ce8:c350 with SMTP id u2csp870435lth; Wed, 14 Sep 2022 09:53:38 -0700 (PDT) X-Google-Smtp-Source: AA6agR4DWT+GoczbLmIJ9DPJjYVZwl6JQlxGygQplJgIfx4NohaAb28Ie3GQOWW1/YktmsEuiUrL X-Received: by 2002:ad4:5c4d:0:b0:4ac:942f:78b0 with SMTP id a13-20020ad45c4d000000b004ac942f78b0mr20724665qva.48.1663174418683; Wed, 14 Sep 2022 09:53:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1663174418; cv=none; d=google.com; s=arc-20160816; b=IxflrsH3sjFzGpyKyk7IF7IIR47GSVj+jMFmg6gOaHaCsQlODnu9sMK+z0SV4cVjU5 OedCGX1Y22rcGx36bro+tJ/1sCO5t9qenQJ0CG3DdsU62XpO0DT3m3IfLpHhOw7o1A+Q CSLSxo7zGWIfSOWUbRRhC3tTVjBxsCJUsHmfyaJGRTGklLvut5Or/dOmelidbSVKPzww Ij5gt1OPxDriIiXUVUnqrmFhbB5ylw/jI12cz/5idKsCaeXIJCNIVY3jhh0IgQ4BaXv1 usyktWlWAPgF91HSqvDAQE4CgalpXKRsuNX54e6MkAUUdVeAfM66EPvps5wSdUBPIfOW hgJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GVr9W2EvQrzSJqGSBV+Z7b6JdNyGZ1lSF1Vl2i4FAiA=; b=OC567Coj29JXmhvf2RT+wzxFxZytsDzZ12fbaDLBODGM9X06qr7XnfR4OvPfPMKSv6 /nHErGZQ6f81DaKASbvGHe3dosbsNvx3O/kGqxR3xF5WcOagBEmTkpJS0dP0DR9GZJim juRAi+PjQ96N3ZB9/ewgJRRYBX7Wp9z4H8FfUOdNfCkpFEArb7wpStkidPKd3Xt83uaz j4QwX98dSnL1X3eAfNXD8j/yB4ReKZtkLC/r9NV4blEwHL90Y9WEAedp3gY7Lc6Rvps8 xrHfRpQd3opnqH6LLr1dvPHq2BU6LiPB3VGUcBUcalURo8StDLbURRH01yjneJgEnv2I vqsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DB87SMj0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j17-20020a05620a411100b006bb465622a2si1996039qko.306.2022.09.14.09.53.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 14 Sep 2022 09:53:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DB87SMj0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50042 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYVdq-0005JJ-5P for patch@linaro.org; Wed, 14 Sep 2022 12:53:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYUxj-0005lO-A1 for qemu-devel@nongnu.org; Wed, 14 Sep 2022 12:10:12 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oYUxe-0004PI-Li for qemu-devel@nongnu.org; Wed, 14 Sep 2022 12:10:05 -0400 Received: by mail-wr1-x435.google.com with SMTP id bz13so26496404wrb.2 for ; Wed, 14 Sep 2022 09:09:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=GVr9W2EvQrzSJqGSBV+Z7b6JdNyGZ1lSF1Vl2i4FAiA=; b=DB87SMj0H3G5KcYfniOmice61S8e+DttWx3ge9vzvta3YpThQs91z1P23bf3+1BHkE /fc0287e03/EzTjFj+GLuaBU0YhO+yVZTbEi5v63L6N3yXfcMRYvBjf0Rrgw08rusBTt azj34x8P4kBe1VBYB/LVGL2CbbSA69NUgpK35YvT3lcY6lHa+zUcqu6Mf+S0IzM3q/+c Asb3zQcH1jIRqu2Qed5JEvswEwFb8G4zPc76KKtP4TDFvTOwaLj1kSTAGUckhKLNY8Ab nkru2P1pyaMLLDJw18hEokN/1KHSZRhidPwLKLjKlXbRGfSiESNzYQ5EFOtNYX3tVOBl 0nGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=GVr9W2EvQrzSJqGSBV+Z7b6JdNyGZ1lSF1Vl2i4FAiA=; b=ZlAczNhnSBvanAzpEYfw4HqpAcPZnB5N3wHLX5F9OU5foLmDvS+MsbzCsj7cfmJa69 VfDkGN04M5BOOIorBVUr2KYaolB167tT2e2mGnGP23jNCJ9FbQldOl9oLbyiasgPgp99 lQ1Pn8iAmU8e9vIcKE16GjnJxiibK2A/jzYMfVt2wRF31bvI+HkfpZwA9h4ojer1aIR9 L+OsscqLD2OrNpnYGMH9vb0+nxMS7CD2P/4cD+nZmfXGNWkO+N7XJZ3mpOBv8B3SzAaY 31kMSKv9wYaD+FA0K8KA7xdaAaKb8Zky4SZ4fz93Oc9stAU0fz4XhJXwFiHRVXHYjlYx niqg== X-Gm-Message-State: ACgBeo0QCrFex0lyr5uA/2JEUCPkkfWdx8fHJrEUvwx4SYTjTwpc3ZbL u8PZpLh6xPr+DwOebatkCiDf3FVa4u9VDS6I X-Received: by 2002:a5d:6301:0:b0:226:d87b:b55c with SMTP id i1-20020a5d6301000000b00226d87bb55cmr20824981wru.560.1663171797713; Wed, 14 Sep 2022 09:09:57 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id l10-20020adfe58a000000b0022863395912sm13314406wrm.53.2022.09.14.09.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Sep 2022 09:09:56 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6AEBB1FFBB; Wed, 14 Sep 2022 17:09:55 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Peter Maydell Subject: [RFC PATCH 3/4] hw/intc/gic: use MxTxAttrs to divine accessing CPU Date: Wed, 14 Sep 2022 17:09:54 +0100 Message-Id: <20220914160955.812151-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220914160955.812151-1-alex.bennee@linaro.org> References: <20220914160955.812151-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that MxTxAttrs encodes a CPU we should use that to figure it out. This solves edge cases like accessing via gdbstub or qtest. Signed-off-by: Alex Bennée Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 Reviewed-by: Richard Henderson --- hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 492b2421ab..7feedac735 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] = { 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; -static inline int gic_get_current_cpu(GICState *s) +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) { - if (!qtest_enabled() && s->num_cpu > 1) { - return current_cpu->cpu_index; - } - return 0; + /* + * Something other than a CPU accessing the GIC would be a bug as + * would a CPU index higher than the GICState expects to be + * handling + */ + g_assert(attrs.requester_cpu == 1); + g_assert(attrs.requester_id < s->num_cpu); + + return attrs.requester_id; } -static inline int gic_get_current_vcpu(GICState *s) +static inline int gic_get_current_vcpu(GICState *s, MemTxAttrs attrs) { - return gic_get_current_cpu(s) + GIC_NCPU; + return gic_get_current_cpu(s, attrs) + GIC_NCPU; } /* Return true if this GIC config has interrupt groups, which is @@ -951,7 +956,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) int cm; int mask; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); cm = 1 << cpu; if (offset < 0x100) { if (offset == 0) { /* GICD_CTLR */ @@ -1182,7 +1187,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, int i; int cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); if (offset < 0x100) { if (offset == 0) { if (s->security_extn && !attrs.secure) { @@ -1476,7 +1481,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset, int mask; int target_cpu; - cpu = gic_get_current_cpu(s); + cpu = gic_get_current_cpu(s, attrs); irq = value & 0xf; switch ((value >> 24) & 3) { case 0: @@ -1780,7 +1785,7 @@ static MemTxResult gic_thiscpu_read(void *opaque, hwaddr addr, uint64_t *data, unsigned size, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, @@ -1788,7 +1793,7 @@ static MemTxResult gic_thiscpu_write(void *opaque, hwaddr addr, MemTxAttrs attrs) { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } /* Wrappers to read/write the GIC CPU interface for a specific CPU. @@ -1818,7 +1823,7 @@ static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data, { GICState *s = (GICState *)opaque; - return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); + return gic_cpu_read(s, gic_get_current_vcpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, @@ -1827,7 +1832,7 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); + return gic_cpu_write(s, gic_get_current_vcpu(s, attrs), addr, value, attrs); } static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start) @@ -1860,7 +1865,7 @@ static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start) static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs) { - int vcpu = gic_get_current_vcpu(s); + int vcpu = gic_get_current_vcpu(s, attrs); uint32_t ctlr; uint32_t abpr; uint32_t bpr; @@ -1995,7 +2000,7 @@ static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *dat { GICState *s = (GICState *)opaque; - return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs); + return gic_hyp_read(s, gic_get_current_cpu(s, attrs), addr, data, attrs); } static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, @@ -2004,7 +2009,7 @@ static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr, { GICState *s = (GICState *)opaque; - return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs); + return gic_hyp_write(s, gic_get_current_cpu(s, attrs), addr, value, attrs); } static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data,