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[209.51.188.17]) by mx.google.com with ESMTPS id m9-20020a05620a24c900b006b920f7b5a2si1366404qkn.702.2022.09.27.08.50.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 27 Sep 2022 08:50:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=POsf1l2Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1odCr1-0004Bt-Qf for patch@linaro.org; Tue, 27 Sep 2022 11:50:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1odBMn-0005A4-3r for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:21 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:46940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1odBMj-00061f-Ox for qemu-devel@nongnu.org; Tue, 27 Sep 2022 10:15:20 -0400 Received: by mail-wr1-x42b.google.com with SMTP id bk15so7472677wrb.13 for ; Tue, 27 Sep 2022 07:15:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9V9LEBkVMIt0gNfbFS+tXVi8Jwwq7HDOfuY//HgX7ok=; b=POsf1l2YOZ4HYa8opijLwGMGJqQhh9MPr1yNJf9NX9Bnao5LC70yNnQtyhrjQ1MAOv WSq6saiyH8qF7SU4PbGQMmpFfWlb00zwiQctj7JukLqe+7KwOLVF3kXNeDo3oKGjR9pp u6KimzDFcGdWJ7EHN/edh0nfPmrclKcmPE1qI6O+MVVy3UJiX3JK7bm5hngQy4eMyiXy mKydhvMlCerMq0bDqmn7knkK7Skzp4uPrCkAcbWkMZHMWlIy0WzxbZ63Ko2Fk2RU8/RU gUw7mpbUt0XrvbioTquu+U22TQ8hh9ykkTHAWSFS/VllPky6aDkj3RWilkFo2rt0HwFf meig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9V9LEBkVMIt0gNfbFS+tXVi8Jwwq7HDOfuY//HgX7ok=; b=zpF9s8oAjj5C1Zk79vffezEJ9JpeSjrFhM2+EulUaow92D9jt2ltTkWE9V/T0StZA1 HD3IY2s8tUY4p6/FiXEQSU83feJwinrQekIQGYvAv+OEiMaYAn2Cblb20ywUYGZ0WxpK FJrsgk0V1rz6AVNC6F6GBaAgryIA7FAMBk11vYGUhJnDNhkX/T50lSZmcUWykKRcKIxf DHEPkQmeCeHp4+fbPVWlT0p6yEFKTAmgI5OSFe60HQgiEDRThR7bxjhniZ5bIIx7DeXS e7Nocs9+ikXHat5wyxOZiIk186mmh5h1XBnsCwJ1KVTNCpBCDLnMJg84mD2Vgmwlp7ZX opnQ== X-Gm-Message-State: ACrzQf3G8z+1LyaUMnSj16GGYmYN6mA4tNB0N4kvvKLCq/JXninjWeGa swqBM6nIC/V1qdmSk7yccXye8w== X-Received: by 2002:a5d:588f:0:b0:22b:623:ad04 with SMTP id n15-20020a5d588f000000b0022b0623ad04mr16915896wrf.607.1664288113769; Tue, 27 Sep 2022 07:15:13 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id p14-20020adfce0e000000b0022af6c93340sm1957085wrn.17.2022.09.27.07.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Sep 2022 07:15:10 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DCC711FFC0; Tue, 27 Sep 2022 15:15:06 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Richard Henderson , Peter Maydell Subject: [PATCH v3 09/15] hw/timer: convert mptimer access to attrs to derive cpu index Date: Tue, 27 Sep 2022 15:14:58 +0100 Message-Id: <20220927141504.3886314-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220927141504.3886314-1-alex.bennee@linaro.org> References: <20220927141504.3886314-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This removes the hacks to deal with empty current_cpu. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé --- v2 - update for new fields - bool asserts --- hw/timer/arm_mptimer.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cdfca3000b..34693a2534 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -41,9 +41,10 @@ * which is used in both the ARM11MPCore and Cortex-A9MP. */ -static inline int get_current_cpu(ARMMPTimerState *s) +static inline int get_current_cpu(ARMMPTimerState *s, MemTxAttrs attrs) { - int cpu_id = current_cpu ? current_cpu->cpu_index : 0; + int cpu_id = attrs.requester_id; + g_assert(attrs.requester_type == MTRT_CPU); if (cpu_id >= s->num_cpu) { hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", @@ -178,25 +179,27 @@ static void timerblock_write(void *opaque, hwaddr addr, /* Wrapper functions to implement the "read timer/watchdog for * the current CPU" memory regions. */ -static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, - unsigned size) +static MemTxResult arm_thistimer_read(void *opaque, hwaddr addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); - return timerblock_read(&s->timerblock[id], addr, size); + int id = get_current_cpu(s, attrs); + *data = timerblock_read(&s->timerblock[id], addr, size); + return MEMTX_OK; } -static void arm_thistimer_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) +static MemTxResult arm_thistimer_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, MemTxAttrs attrs) { ARMMPTimerState *s = (ARMMPTimerState *)opaque; - int id = get_current_cpu(s); + int id = get_current_cpu(s, attrs); timerblock_write(&s->timerblock[id], addr, value, size); + return MEMTX_OK; } static const MemoryRegionOps arm_thistimer_ops = { - .read = arm_thistimer_read, - .write = arm_thistimer_write, + .read_with_attrs = arm_thistimer_read, + .write_with_attrs = arm_thistimer_write, .valid = { .min_access_size = 4, .max_access_size = 4,