From patchwork Thu Oct 6 03:38:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 612872 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1204304pvb; Wed, 5 Oct 2022 20:52:45 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5IDxyXC4VW/fV7o6WYFvOw7THu15Ha2w0PTife2lKj+IourVBb4Gz6XV6K+2F1dcFCiWhb X-Received: by 2002:a05:620a:444a:b0:6ce:9917:ea1e with SMTP id w10-20020a05620a444a00b006ce9917ea1emr1898816qkp.399.1665028365673; Wed, 05 Oct 2022 20:52:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665028365; cv=none; d=google.com; s=arc-20160816; b=y7zk1Lf6V7w6+ALCpPJE7wIzWBECoqvuKZRSe/0dq6/YOsMvsaHSs1djjjqxHmud+H mNu5rhZ70vq7VsS0K+Gd8Op796DILnSCa9TpF/qOqXSgDdCUh8GsXh4J2vraWJHP/iub h44FJKH12trI3u/43YvwoAR90cyaxsrwT/APFfeWH+VqBNPaZFi3k5K8mrutysLP/g8J 7NqyW4AF52H5xLdpDR0BxbPmoXwv6GIujpXqB8pL4ZUMdQhk5I1RN5oEsPpPx3BQexFd MLLK7hhYQkSW45PDHhyzOJpiOVZ7n15/T6r51yGoF7cIMmBPA6BtREomLxovWlyIGaEH VbBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+B8rOtkjvONjZSA2MWgoQbv6N8UN3QaAqQ4YsJ87nAo=; b=tEh3taQaxkh1jx0frnYDEMUa3tcX9kO3EBBqfKveUF9GpRoVX3p4nayFZAENXSq0uH /p/iPoi11gpMlZzlWBMTsy5OQSDnRKKiMG4qkVnuBw5omT2H9zjmxQAwiy/2X0r+7t1D tKEa2enea3S6ohcsfprbzaKtcbKrp2hz9lbuV7ON+pKoMBBQ6rsrzJYjIsF69mK5RP6O hg4f2kTiIdMyQrKGVd6Zx3xp69cCi3ZLo8trgdcbdBE6lW9IZTphqOEH+nsv3Yj8ECsJ fgKQd2kBwqysHFxBNQ+wuE42aabfE34elBWto4XwEp4+eDkch6vFyxtMOCErm0sIhIyO HCgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VeMHYJJX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p10-20020a05621421ea00b004b203c9b388si13643qvj.309.2022.10.05.20.52.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 05 Oct 2022 20:52:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VeMHYJJX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:33110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ogHwD-00023s-2w for patch@linaro.org; Wed, 05 Oct 2022 23:52:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ogHiv-00035p-88 for qemu-devel@nongnu.org; Wed, 05 Oct 2022 23:39:01 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:46998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ogHiq-0002uH-36 for qemu-devel@nongnu.org; Wed, 05 Oct 2022 23:39:00 -0400 Received: by mail-pj1-x1034.google.com with SMTP id t12-20020a17090a3b4c00b0020b04251529so523819pjf.5 for ; Wed, 05 Oct 2022 20:38:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=+B8rOtkjvONjZSA2MWgoQbv6N8UN3QaAqQ4YsJ87nAo=; b=VeMHYJJXI/putB8ubSzkEUP+cy7ySOBaJAlEk7C4Tz6CF2qsxPCu0ExaLO0To+IuEc qwbn5bvQ6yXc43Lu+rCKAhJ7J9AV2XVy2Sy7M9TJZNNI8JAHQc7R5wWIhD6cmehsxcDg nBtpGQMAv6ptHJHyJ81P9zV/8s+d/teQ9dRRSLlqIjJa+yE+nVDqh0rZr/q8hGRKX3r6 NkYPenAaLq5lL66ShISw3yJZ0+OCZtMZ3WglNvL3p5SutzTE8lN1Qr4s54BD1ydiWam2 Qk/IsdQkBK7Nwi2VA3v0HFIcynV0n6pdMKIPnYrbhD8Hvn7g3ZoqmtTs4YBCr2g0iYZC ajOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=+B8rOtkjvONjZSA2MWgoQbv6N8UN3QaAqQ4YsJ87nAo=; b=Fr7VLqJpLk7esnhOYZ0a91c0V84aknFWH/U33MFO3Afw3/cVfBKJIYmZ6nm8AFTZV2 jpznoq9nDOAGDIaAEsbSEgxtqzOVhLeEXB/krWclQddU65GbVXCgMgT6Dxljpdxr+qS9 YTcN9hFbjDJ3UIKkGO+MGrDLJDvIzK5LhAmPhJQur9lE6sA2oxUd/TmpA+r+5LdRdIFI DPbsp2mJ3zNz6TN9495L0smsFKsPfRh0+5IqbbZ+QtxWJdMo6PsPplA2X3PzXJDn5CZk ZOWE2XkH22Y0A9AxlOBE7FpQhl078icz5GIZ0QlR+Ez4/EdbYBg6GC7YZIbg8H05ovs4 InxA== X-Gm-Message-State: ACrzQf3iJdD7z4Y1S49kgP/Da/gD2VtckTE/hbpN7WnetR50bJkAZBFz UnUKAHrn7w0S8lHIBZ2g7WSdzbkhIy1t2w== X-Received: by 2002:a17:902:d2c2:b0:177:ed66:798 with SMTP id n2-20020a170902d2c200b00177ed660798mr2604235plc.76.1665027529565; Wed, 05 Oct 2022 20:38:49 -0700 (PDT) Received: from stoup.. ([2602:47:d49d:ec01:9ad0:4307:7d39:bb61]) by smtp.gmail.com with ESMTPSA id t11-20020a63534b000000b0043014f9a4c9sm539831pgl.93.2022.10.05.20.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 20:38:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 2/9] target/arm: Change gen_goto_tb to work on displacements Date: Wed, 5 Oct 2022 20:38:39 -0700 Message-Id: <20221006033846.1178422-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221006033846.1178422-1-richard.henderson@linaro.org> References: <20221006033846.1178422-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for TARGET_TB_PCREL, reduce reliance on absolute values. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 40 ++++++++++++++++++++------------------ target/arm/translate.c | 10 ++++++---- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 78b2d91ed4..8f5c2675f7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -378,8 +378,10 @@ static inline bool use_goto_tb(DisasContext *s, uint64_t dest) return translator_use_goto_tb(&s->base, dest); } -static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) +static void gen_goto_tb(DisasContext *s, int n, int64_t diff) { + uint64_t dest = s->pc_curr + diff; + if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_a64_set_pc_im(dest); @@ -1362,7 +1364,7 @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, */ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) { - uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4; + int64_t diff = sextract32(insn, 0, 26) * 4; if (insn & (1U << 31)) { /* BL Branch with link */ @@ -1371,7 +1373,7 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) /* B Branch / BL Branch with link */ reset_btype(s); - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } /* Compare and branch (immediate) @@ -1383,14 +1385,14 @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) static void disas_comp_b_imm(DisasContext *s, uint32_t insn) { unsigned int sf, op, rt; - uint64_t addr; + int64_t diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; sf = extract32(insn, 31, 1); op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ rt = extract32(insn, 0, 5); - addr = s->pc_curr + sextract32(insn, 5, 19) * 4; + diff = sextract32(insn, 5, 19) * 4; tcg_cmp = read_cpu_reg(s, rt, sf); label_match = gen_new_label(); @@ -1399,9 +1401,9 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } /* Test and branch (immediate) @@ -1413,13 +1415,13 @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn) static void disas_test_b_imm(DisasContext *s, uint32_t insn) { unsigned int bit_pos, op, rt; - uint64_t addr; + int64_t diff; TCGLabel *label_match; TCGv_i64 tcg_cmp; bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ - addr = s->pc_curr + sextract32(insn, 5, 14) * 4; + diff = sextract32(insn, 5, 14) * 4; rt = extract32(insn, 0, 5); tcg_cmp = tcg_temp_new_i64(); @@ -1430,9 +1432,9 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, tcg_cmp, 0, label_match); tcg_temp_free_i64(tcg_cmp); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } /* Conditional branch (immediate) @@ -1444,13 +1446,13 @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn) static void disas_cond_b_imm(DisasContext *s, uint32_t insn) { unsigned int cond; - uint64_t addr; + int64_t diff; if ((insn & (1 << 4)) || (insn & (1 << 24))) { unallocated_encoding(s); return; } - addr = s->pc_curr + sextract32(insn, 5, 19) * 4; + diff = sextract32(insn, 5, 19) * 4; cond = extract32(insn, 0, 4); reset_btype(s); @@ -1458,12 +1460,12 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn) /* genuinely conditional branches */ TCGLabel *label_match = gen_new_label(); arm_gen_test_cc(cond, label_match); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); gen_set_label(label_match); - gen_goto_tb(s, 1, addr); + gen_goto_tb(s, 1, diff); } else { /* 0xe and 0xf are both "always" conditions */ - gen_goto_tb(s, 0, addr); + gen_goto_tb(s, 0, diff); } } @@ -1637,7 +1639,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * any pending interrupts immediately. */ reset_btype(s); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; case 7: /* SB */ @@ -1649,7 +1651,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * MB and end the TB instead. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->base.pc_next); + gen_goto_tb(s, 0, 4); return; default: @@ -14955,7 +14957,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, 4); break; default: case DISAS_UPDATE_EXIT: diff --git a/target/arm/translate.c b/target/arm/translate.c index 42e11102f7..6855128fb1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2594,8 +2594,10 @@ static void gen_goto_ptr(void) * cpu_loop_exec. Any live exit_requests will be processed as we * enter the next TB. */ -static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) +static void gen_goto_tb(DisasContext *s, int n, int diff) { + target_ulong dest = s->pc_curr + diff; + if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); @@ -2629,7 +2631,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno) * gen_jmp(); * on the second call to gen_jmp(). */ - gen_goto_tb(s, tbno, dest); + gen_goto_tb(s, tbno, dest - s->pc_curr); break; case DISAS_UPDATE_NOCHAIN: case DISAS_UPDATE_EXIT: @@ -9798,7 +9800,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_TOO_MANY: - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); break; case DISAS_UPDATE_NOCHAIN: gen_set_pc_im(dc, dc->base.pc_next); @@ -9850,7 +9852,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_set_pc_im(dc, dc->base.pc_next); gen_singlestep_exception(dc); } else { - gen_goto_tb(dc, 1, dc->base.pc_next); + gen_goto_tb(dc, 1, curr_insn_len(dc)); } } }