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([2602:47:d49d:ec01:5aa4:aba1:1c91:a9b7]) by smtp.gmail.com with ESMTPSA id o74-20020a62cd4d000000b0055f209690c0sm7663567pfg.50.2022.10.10.20.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 20:20:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 23/24] target/arm: Implement FEAT_HAFDBS, dirty bit portion Date: Mon, 10 Oct 2022 20:19:10 -0700 Message-Id: <20221011031911.2408754-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011031911.2408754-1-richard.henderson@linaro.org> References: <20221011031911.2408754-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Perform the atomic update for hardware management of the dirty bit. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 2 +- target/arm/ptw.c | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fe1369fe96..0732796559 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1165,7 +1165,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; - t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 1); /* FEAT_HAFDBS, AF only */ + t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 82b6ab029e..0dbbb7d4d4 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1484,10 +1484,30 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, ap = extract32(attrs, 6, 2); if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) { + if (param.hd + && extract64(attrs, 51, 1) /* DBM */ + && access_type == MMU_DATA_STORE) { + /* + * Pre-emptively set S2AP[1], so that we compute EXEC properly. + * C.f. AArch64.S2ApplyOutputPerms, which does the same thing. + */ + ap |= 2; + new_descriptor |= 1ull << 7; + } ns = mmu_idx == ARMMMUIdx_Stage2; xn = extract64(attrs, 54, 2); result->f.prot = get_S2prot(env, ap, xn, s1_is_el0); } else { + if (param.hd + && extract64(attrs, 51, 1) /* DBM */ + && access_type == MMU_DATA_STORE) { + /* + * Pre-emptively clear AP[2], so that we compute EXEC properly. + * C.f. AArch64.S1ApplyOutputPerms, which does the same thing. + */ + ap &= ~2; + new_descriptor &= ~(1ull << 7); + } ns = extract32(attrs, 5, 1); xn = extract64(attrs, 54, 1); pxn = extract64(attrs, 53, 1);