From patchwork Thu Nov 24 11:50:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 628326 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp301421pvb; Thu, 24 Nov 2022 03:59:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf7Q9VJOOvu6KfEguPz2BUdzj3KPRgJ1ZPOkeIQ9ZJQ4Zt7F2A/Gj375aasBJVb5o2ohxJdT X-Received: by 2002:a37:92c6:0:b0:6f9:f247:8864 with SMTP id u189-20020a3792c6000000b006f9f2478864mr11765046qkd.100.1669291175156; Thu, 24 Nov 2022 03:59:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669291175; cv=none; d=google.com; s=arc-20160816; b=MUDefG7WySGhE9SvcozWdTEq0Zvjeyusica7mAJn3T4q4nk3QNzRiJLvLcVJo0Uyr2 Rhb+ios+CWA5+jp7kHTvX/h6nYJWARY6Po/syWt2EuKsiHNFUb2TN//bhj/8AhGyf5Vn TO3nQ8ObBByFYNt34lyHmfvr+p6vg0SOgx4OPKqRo1+45gr8d8hNF9r494/mC+swFQ3V wc0RLAypekG2Ym8ik9LfDPs2yPFeRSxaKHNg7OFwwU5GjynCvUT9BHIhwwv2hfhrHmbI ExuCuPIi9TultR/8prewn5vSP9GFt8y30BaheAKSkwPaCP51VD8ImjTDdjOVWm+e8OpC V8dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6ZF6j0QSh9sYA2HgkILcyWukmhzzkxCNhgIX/8WMk28=; b=gOZ5Gpst96E/s/7znqSXIUOjGmOtYmakkzyhg+A/44MXSLGRFBZsbbvKuYoX/JY+w9 WbXKjQ6khu/joWjQHdmOyfjy7k1lkr42EKkWXpbIL0iaMuXx6tdFEPN42wNFbmUvHHvH kX/6bl6GEfcQ8oefceC3PI42MbfcT2/9FPO8ZW7h8xl6wR+0TnVenAUNke2kQdbZVHnd 5dzHKJj2wisGzoowMN3JKgvCR/kmIQ68EUXdb4vETlN67lDckA+yM/3Y6zKy8EKW391L Vr7WokFORyBOKJq3aV5rNeB9fsX1mt/FCw7Wq5YU19u+msM0uiN5p11CnyEFZauNoFK9 L4PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NAT4FHh2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r11-20020ae9d60b000000b006cec0749c1bsi588686qkk.306.2022.11.24.03.59.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 24 Nov 2022 03:59:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NAT4FHh2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oyAko-0003hZ-6F; Thu, 24 Nov 2022 06:50:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oyAkd-0003Wr-FW for qemu-devel@nongnu.org; Thu, 24 Nov 2022 06:50:45 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oyAkX-0004rJ-Tp for qemu-devel@nongnu.org; Thu, 24 Nov 2022 06:50:42 -0500 Received: by mail-wr1-x434.google.com with SMTP id cl5so2106793wrb.9 for ; Thu, 24 Nov 2022 03:50:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6ZF6j0QSh9sYA2HgkILcyWukmhzzkxCNhgIX/8WMk28=; b=NAT4FHh2y5rfoCsN2LOyaBHUjKRRBGr4i2n+kh6KKWC9FTpJO2uKeVXKlXd67RYKfP 1OcT1jIORmWT+rkZaYG4r9ZM2pMa75XvwYxq4h2d5Js4HqalHq4Dy3f7Kp91qEBiaVex hlc+82YG/1xfezhc/951gCNyri7JysQt4mpLodDf+8gGXagB5G+wnRrNXq4Cj5jrn/4V XGO0xAHBZRDm4JAjovVfnk1Ln4iic7UR+VoiwK7kh6b2lLsJFHWmqKQ4M3yIuTeGuG9A 3CTA2in20ok/RxmkqYkVC/t7NMgwNqHrA/FrEWkeJS+MilCaJtjPjWeByuGIfuxM7o9x XWsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6ZF6j0QSh9sYA2HgkILcyWukmhzzkxCNhgIX/8WMk28=; b=ANEuDB15aPmPH1TdgQ3Kdpiv+gN0sTpE1CRFDVsaoBkkUb3lqPqJo1fzN2/ccsDKHP ZJsaaFNfmINIthsgxFKTgLqryZGg4qaBlhtc84+OxWtcRXXZRyB9IyTFh3ExccCXkwni QScjBiMgX2/PeWwwskPKAZM5hxCGUKeqLBQEpTHiBNijTCoftBqGLYNvUHtmC4Wezvmv bpmTslnMFAyDNRW0dRLG8hZaEYczkloDuGuPFu3ZTD0z18E2H6/A/D/mz1jSGv8tg/R0 gAmWnIZCfs8mPsKz+Qo8tkesgo69Q0lQt+cNRDsYt/3natPT7oPDXac9zDAxghEaTOzI vKFQ== X-Gm-Message-State: ANoB5pmr/cZ+9WB57Bf9+QJXl7x+gZkY0q9GyQyvtNYwKQoRtySn+W5j PgTvdrPC35OWTVr2UvAv3LCnxAr4GwzeoQ== X-Received: by 2002:a05:6000:12c7:b0:241:c876:773c with SMTP id l7-20020a05600012c700b00241c876773cmr14540856wrx.95.1669290637064; Thu, 24 Nov 2022 03:50:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f14-20020a05600c154e00b003c6f3e5ba42sm6212559wmg.46.2022.11.24.03.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Nov 2022 03:50:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Taylor Simpson , Song Gao , Xiaojuan Yang , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Chris Wulff , Marek Vasut , Stafford Horne , Daniel Henrique Barboza , =?utf-8?q?C=C3=A9dric_Le_G?= =?utf-8?q?oater?= , David Gibson , Greg Kurz , Palmer Dabbelt , Alistair Francis , Bin Meng , Yoshinori Sato , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH for-8.0 07/19] target/loongarch: Convert to 3-phase reset Date: Thu, 24 Nov 2022 11:50:10 +0000 Message-Id: <20221124115023.2437291-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221124115023.2437291-1-peter.maydell@linaro.org> References: <20221124115023.2437291-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the loongarch CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell --- target/loongarch/cpu.h | 4 ++-- target/loongarch/cpu.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index e15c633b0bf..e35cf655975 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -356,7 +356,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, /** * LoongArchCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * A LoongArch CPU model. */ @@ -366,7 +366,7 @@ struct LoongArchCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; }; /* diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 46b04cbdad1..e8c42f17a54 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -452,14 +452,16 @@ void loongarch_cpu_list(void) g_slist_free(list); } -static void loongarch_cpu_reset(DeviceState *dev) +static void loongarch_cpu_reset_hold(Object *obj) { - CPUState *cs = CPU(dev); + CPUState *cs = CPU(obj); LoongArchCPU *cpu = LOONGARCH_CPU(cs); LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu); CPULoongArchState *env = &cpu->env; - lacc->parent_reset(dev); + if (lacc->parent_phases.hold) { + lacc->parent_phases.hold(obj); + } env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3; env->fcsr0 = 0x0; @@ -696,10 +698,12 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c); + ResettableClass *rc = RESETTABLE_CLASS(c); device_class_set_parent_realize(dc, loongarch_cpu_realizefn, &lacc->parent_realize); - device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, loongarch_cpu_reset_hold, NULL, + &lacc->parent_phases); cc->class_by_name = loongarch_cpu_class_by_name; cc->has_work = loongarch_cpu_has_work;