From patchwork Fri Dec 16 21:42:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634452 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1079344pvb; Fri, 16 Dec 2022 14:09:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf5q2avLURHb1Bnb69Phfrq+B2mKtxjOGaQ6Qw1cClCh9dtxtaFvm9vnVEbK4UIzUHoFqPpa X-Received: by 2002:a05:6122:e42:b0:3be:21e0:5dfe with SMTP id bj2-20020a0561220e4200b003be21e05dfemr16084379vkb.0.1671228575215; Fri, 16 Dec 2022 14:09:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671228575; cv=none; d=google.com; s=arc-20160816; b=OU6kv5eQQFbPipFAsSKGMuaq1EINVKtQd7HjkF1y+7TIDDX4qL3uf5J4D3D0TAiWAr Dn4mJwrY+bjepwV3XGROVvmTAktvVQ/0QiIUjbCZJV12vBsNV5pgQAXeFtge/iGsD/+Q T/Y9nPq0+mnHzYQO6PD5oFnVhW49rupHBKf1EvkH30e7qJTEY+pvg4cjyuIIOUf3lD5r JrP3gFwRU6TsMHpqL42RJgB027vm2hmUXZT4U+oe2qahv+K5D9ZPbisHKYL0T/czCILk Lqtps3TFD3MFE6hT/FBL+I90VFiF9qU/EXOiwg6in2Iym3BMb5qvG4c9xZvJkA1pOMzM WKuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=q8tZDsND3tybaP48R6M+gEKoRel5tUUnDBAqMV6lK9Q=; b=tkKreCSqfnl7rw7pumM9tmKQW/lgJrfKZAuZvKILpv5RTv3wnTyBThp459Bj97FkPx RAZ+0qFjUDUgwLhL/8KPEgV9qkKAxbJHtdeZaPlsQn1hmqcULB+Jii7rkMTrHxfExehN +Ca4MaON27z3bPPXDlBSVJOPusercnQWr/OpTzJkB+VnwSbphjPm8FFvT3UnAiQ5weHP 9A6Hhx6+DT8x8goji+62KW0agpGti07oVOSI+iH+ml+4HCaXoKAdpZZ0xflpzrnUD3bh JDEykfQJ+aQpcwMUHmsmPgxlJ//JM4VsTZQayii2DpmOeZf9mRMzOFWnpB+UpoJaB69M wN8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EfjNw6lL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u3-20020ae9c003000000b006fca0358d87si1466179qkk.239.2022.12.16.14.09.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Dec 2022 14:09:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EfjNw6lL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p6IU2-00060x-T6; Fri, 16 Dec 2022 16:43:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p6ITu-0005wq-IP for qemu-devel@nongnu.org; Fri, 16 Dec 2022 16:43:06 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p6ITs-0000ea-P6 for qemu-devel@nongnu.org; Fri, 16 Dec 2022 16:43:02 -0500 Received: by mail-wm1-x32d.google.com with SMTP id bi26-20020a05600c3d9a00b003d3404a89faso1997512wmb.1 for ; Fri, 16 Dec 2022 13:43:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=q8tZDsND3tybaP48R6M+gEKoRel5tUUnDBAqMV6lK9Q=; b=EfjNw6lLQ7hF6jJDimXg59ek5raX471SFaougtz/J6/qx3/dk8eIHkCB7Tma4zLBOQ +GomQ3uBMM6PHaQf3nvFLWHRcKHZZHhYXkLLruIPh8DVp7zWrl6zEEUK8YVypbceI8es ISSngj/3F5005JvE7/WfuRi3sbiMidwk+K0txKaxHhf8yfwiH67icNNQigy1xHS8PfhN Zsv6QQ4wUrR3zXcJSvCIkUoSbsXV9rqvNPSUBugvqIEpt1Dup54jf/psbiBX+jByQXs7 Cv4CAgpxA/6RL4qV5xA5Qnh6eW/9TkmFkIYtv0ER3hd8uQzTGhxCOMHLsLcRmTLe58Lu I9JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q8tZDsND3tybaP48R6M+gEKoRel5tUUnDBAqMV6lK9Q=; b=rwUTXFVNZOYKbv5FO6gF3xnhRPepPaYg+xMstd7TXC0UTQK4CBPCroG8ZAJq+l170R GhYKpvJcUVZNUl7hiLRrrFcbqFnyW+4X5a1Htl3dF4+mf9N8P5nJfpd32BRT0GQvyrRC mjQVJoeZb7fnEQ539AadhXgE0DRgTF5L8te+TVM9jNFXiKkhtBgN/mCWDCQtRWyMy7Wx aRMu1xy6MOzwRTW3PVlGMmxCSVcfi3fgsvU9jL205FjRuwNDf9UFKXNGjHSy98ZDw6aH zVZ0XK5+rsbixSVxe/i5WFEr1Nr5+zRwboeq6I6+cO2IwnKyfLartOsDZG318d9OGSMf RCJQ== X-Gm-Message-State: ANoB5pl4hGWl3SJoKf2RMMK7AuZd4iBqucgTmn3Ryexf79E+u00RmH4N fHGjjEfhcuCGrNa1PbaCBPnv/qtT3xlzNIud X-Received: by 2002:a05:600c:3b93:b0:3d2:3e75:7bb9 with SMTP id n19-20020a05600c3b9300b003d23e757bb9mr8073893wms.34.1671226979235; Fri, 16 Dec 2022 13:42:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a05600c364700b003d33ab317dasm4135263wmq.14.2022.12.16.13.42.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:42:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/36] target/cris: Convert to 3-phase reset Date: Fri, 16 Dec 2022 21:42:22 +0000 Message-Id: <20221216214244.1391647-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221216214244.1391647-1-peter.maydell@linaro.org> References: <20221216214244.1391647-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the cris CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Cédric Le Goater Reviewed-by: Edgar E. Iglesias Message-id: 20221124115023.2437291-5-peter.maydell@linaro.org --- target/cris/cpu-qom.h | 4 ++-- target/cris/cpu.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 71e8af0e70a..431a1d536a9 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) /** * CRISCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * @vr: Version Register value. * * A CRIS CPU model. @@ -41,7 +41,7 @@ struct CRISCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; uint32_t vr; }; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index fb05dc6f9ab..a6a93c23595 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -56,15 +56,17 @@ static bool cris_cpu_has_work(CPUState *cs) return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } -static void cris_cpu_reset(DeviceState *dev) +static void cris_cpu_reset_hold(Object *obj) { - CPUState *s = CPU(dev); + CPUState *s = CPU(obj); CRISCPU *cpu = CRIS_CPU(s); CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); CPUCRISState *env = &cpu->env; uint32_t vr; - ccc->parent_reset(dev); + if (ccc->parent_phases.hold) { + ccc->parent_phases.hold(obj); + } vr = env->pregs[PR_VR]; memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); @@ -305,11 +307,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); device_class_set_parent_realize(dc, cris_cpu_realizefn, &ccc->parent_realize); - device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL, + &ccc->parent_phases); cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work;