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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a05600c364700b003d33ab317dasm4135263wmq.14.2022.12.16.13.43.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:43:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/36] target/mips: Convert to 3-phase reset Date: Fri, 16 Dec 2022 21:42:28 +0000 Message-Id: <20221216214244.1391647-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221216214244.1391647-1-peter.maydell@linaro.org> References: <20221216214244.1391647-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the mips CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Cédric Le Goater Reviewed-by: Edgar E. Iglesias Reviewed-by: Taylor Simpson Message-id: 20221124115023.2437291-11-peter.maydell@linaro.org --- target/mips/cpu-qom.h | 4 ++-- target/mips/cpu.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index e28b5296073..0dffab453b2 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) /** * MIPSCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * A MIPS CPU model. */ @@ -44,7 +44,7 @@ struct MIPSCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; const struct mips_def_t *cpu_def; /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 7a565466cb3..c614b04607a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -182,14 +182,16 @@ static bool mips_cpu_has_work(CPUState *cs) #include "cpu-defs.c.inc" -static void mips_cpu_reset(DeviceState *dev) +static void mips_cpu_reset_hold(Object *obj) { - CPUState *cs = CPU(dev); + CPUState *cs = CPU(obj); MIPSCPU *cpu = MIPS_CPU(cs); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; - mcc->parent_reset(dev); + if (mcc->parent_phases.hold) { + mcc->parent_phases.hold(obj); + } memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); @@ -562,10 +564,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); CPUClass *cc = CPU_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c); + ResettableClass *rc = RESETTABLE_CLASS(c); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); - device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, + &mcc->parent_phases); cc->class_by_name = mips_cpu_class_by_name; cc->has_work = mips_cpu_has_work;