From patchwork Fri Dec 16 21:42:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 634497 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp1088091pvb; Fri, 16 Dec 2022 14:32:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf6L1Lr6OYEyt/N/sxY4uCer+4+5AMlLA0O98xzEwTxvX3YWCulC/dKP3kf6jO8SV2XKQIcu X-Received: by 2002:a05:622a:91:b0:3a8:133a:9686 with SMTP id o17-20020a05622a009100b003a8133a9686mr45056129qtw.12.1671229922111; Fri, 16 Dec 2022 14:32:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671229922; cv=none; d=google.com; s=arc-20160816; b=gDEdp0p7wIUXkZpkia+DSisf25MJLs7pv5xhqlMiBlxWMKUTYN4gPIiPHXSX7iQ3oI /T4Gd95r85/63cWxlN0iBhI1L6x60WOkG4eqRLtZKzw8cXHL5mVjcj7589GabNPBbGD8 ou8z4e9UKr2n9wUvlIzBKm38V4tSm6T/ONMKYQBI+8fU1MrLU2AuqP8i/+OJCr+yUlKp L58Gvj9B6DTkN6+gbK4ySxsS9uDQhuYWpL/38ONNnS7QsRkZp5sgh9ZxkqYo2embCM2P 6s3I5TJxXFJFtd7bUR8eYBr5Mr47hohzWZL2Vf5juZ3rTmaYIVKOw9YwMFCEHdpmssWx TC5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OaolEeI/VBAVtDjg7jIzycyq6Q1jqs6WjWVYeKLQJ68=; b=vlrik3G983/odPD2OeV7d1YaZ/S68vuA3jfG6BSfoL6/Pcwqz6qITM70HNL+aatT6b z9ZB9+9eRyf/mrlBk1b94/ZRbDCoRomRw7j7acs9snw71a3dV7x4PcgYpm0VJ3tapkUQ cqsLDiR3hpTlE3L53qdfzqfuIgaUOcuI8uqxynYJUv4pF4yM/Gvgkl2Sp1DeBUHcuU+N 8Tl/fOwC6IpnzhEAptrLhV9RLJZADuPDaV9+ywrDWx1mYqSO4JYdn3D9abjMmS5ZKRJv yn3xoJoHOZAA6en4tF4/93iIL3UfLBZcHGFB4y7XbBIkSu3JEzuoVC5sfWPA9YUx+WAW v+TA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OhHIdHLw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j12-20020ac8550c000000b0039461d2ca93si1443907qtq.523.2022.12.16.14.32.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 16 Dec 2022 14:32:02 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OhHIdHLw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p6IUq-0006Zb-MD; Fri, 16 Dec 2022 16:44:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p6IU4-00061g-Fg for qemu-devel@nongnu.org; Fri, 16 Dec 2022 16:43:12 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p6IU2-0000cM-MX for qemu-devel@nongnu.org; Fri, 16 Dec 2022 16:43:12 -0500 Received: by mail-wm1-x330.google.com with SMTP id o5-20020a05600c510500b003d21f02fbaaso4980895wms.4 for ; Fri, 16 Dec 2022 13:43:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=OaolEeI/VBAVtDjg7jIzycyq6Q1jqs6WjWVYeKLQJ68=; b=OhHIdHLwNyH0CsC6iNDJuXMoEAHDtz8QuHhzMKd0GLMIzpW7N0XrnSGPzC5gBaNcxL 6kAFZ7lBVN0vybG85Puxq++alFqsfLDBo6XZlbA1ocn23gIsIe2ETGdXcewAu1ZiDlfu bPW9KDprDuVeraTIVVpPSHHXNcTfWw03MZixxy6QmcrC5ye3LPA8KmlZPiv/5r8F/gDo wqK5NwhQ7oBTqkV2XksEqQclud70Ax9XRKK2mUrZUlOuwwXrhk4AYaagnNXTt17p/PBE qwuOGDw/ayaCB/zFKMU84FcKAUF9J4IA5eb9Vdq2QE2CGhP5uyd70aLCuABbNk8mPZIS rO1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OaolEeI/VBAVtDjg7jIzycyq6Q1jqs6WjWVYeKLQJ68=; b=HEXRSyT0XnZfHaGf6QQy+b3NP6cykZHlO+Yv2j5Ga8UwW2rGVZP4eRhyunTLdbVIVq nhGRfNP86VJXFdloBcCsb3IHxAFozG4CRGumxLL+eVlgxU72J4pbGq/E3qw0kLHfxf6B vz3G2akb00uEXYPexyRRj6vyiCgDfSHEaAOjWcbnttsU0Zmxt8NaegxrQUFry/1j412D vLiSSoj8n+BvN7pB85ui14RJVokYp53zvZNA3XbpQdlXB5w5fDKUbOc1XU5B1lVhlicf myaIbAaWtJZtburYOXmFWThkI/MehgjHMH0vWcd87UAK4lgeLoNBRE7dVBevdO5QK56O 2mHg== X-Gm-Message-State: ANoB5pkxG1NCaX4lYXrNNk9v8KGLTi4VvqklJZpr6z/4SPsCK+MqPFsi 5wpPczonyy1mMkCjtAk+E2PTRr/aezofcN7G X-Received: by 2002:a1c:cc1a:0:b0:3cf:5583:8b3f with SMTP id h26-20020a1ccc1a000000b003cf55838b3fmr27369970wmb.20.1671226989952; Fri, 16 Dec 2022 13:43:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id y7-20020a05600c364700b003d33ab317dasm4135263wmq.14.2022.12.16.13.43.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 13:43:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/36] target/rx: Convert to 3-phase reset Date: Fri, 16 Dec 2022 21:42:33 +0000 Message-Id: <20221216214244.1391647-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221216214244.1391647-1-peter.maydell@linaro.org> References: <20221216214244.1391647-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the rx CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Cédric Le Goater Reviewed-by: Edgar E. Iglesias Reviewed-by: Taylor Simpson Reviewed-by: Greg Kurz Message-id: 20221124115023.2437291-16-peter.maydell@linaro.org --- target/rx/cpu-qom.h | 4 ++-- target/rx/cpu.c | 13 ++++++++----- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 4533759d966..1c8466a1870 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -31,7 +31,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) /* * RXCPUClass: * @parent_realize: The parent class' realize handler. - * @parent_reset: The parent class' reset handler. + * @parent_phases: The parent class' reset phase handlers. * * A RX CPU model. */ @@ -41,7 +41,7 @@ struct RXCPUClass { /*< public >*/ DeviceRealize parent_realize; - DeviceReset parent_reset; + ResettablePhases parent_phases; }; #endif diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 9003c6e9fed..219ef28e463 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -62,14 +62,16 @@ static bool rx_cpu_has_work(CPUState *cs) (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } -static void rx_cpu_reset(DeviceState *dev) +static void rx_cpu_reset_hold(Object *obj) { - RXCPU *cpu = RX_CPU(dev); + RXCPU *cpu = RX_CPU(obj); RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu); CPURXState *env = &cpu->env; uint32_t *resetvec; - rcc->parent_reset(dev); + if (rcc->parent_phases.hold) { + rcc->parent_phases.hold(obj); + } memset(env, 0, offsetof(CPURXState, end_reset_fields)); @@ -215,11 +217,12 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); CPUClass *cc = CPU_CLASS(klass); RXCPUClass *rcc = RX_CPU_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); device_class_set_parent_realize(dc, rx_cpu_realize, &rcc->parent_realize); - device_class_set_parent_reset(dc, rx_cpu_reset, - &rcc->parent_reset); + resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL, + &rcc->parent_phases); cc->class_by_name = rx_cpu_class_by_name; cc->has_work = rx_cpu_has_work;