Message ID | 20230113154532.49979-26-philmd@linaro.org |
---|---|
State | Accepted |
Commit | 1953dfa80e0fc44a8ccfc97b4ada941e9383bba7 |
Headers | show
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Tsirkin" <mst@redhat.com> Subject: [PULL 25/46] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Date: Fri, 13 Jan 2023 16:45:11 +0100 Message-Id: <20230113154532.49979-26-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230113154532.49979-1-philmd@linaro.org> References: <20230113154532.49979-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org |
Series |
[PULL,01/46] hw/mips/malta: Split FPGA LEDs/ASCII display updates
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diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9fc3280407..ae76b4db70 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -621,6 +621,10 @@ static void network_init(PCIBus *pci_bus) static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, uint64_t kernel_entry) { + static const char pci_pins_cfg[PCI_NUM_PINS] = { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; + /* Bus endianess is always reversed */ #if TARGET_BIG_ENDIAN #define cpu_to_gt32 cpu_to_le32 @@ -659,6 +663,20 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, #undef cpu_to_gt32 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(p, true, ENVP_VADDR - 64, /*