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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id 2-20020a170902c10200b00189743ed3b6sm91468pli.64.2023.02.21.18.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Feb 2023 18:00:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Pierrick Bouvier Subject: [PULL v2 7/8] util/cacheflush: fix cache on windows-arm64 Date: Tue, 21 Feb 2023 16:00:22 -1000 Message-Id: <20230222020023.904232-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222020023.904232-1-richard.henderson@linaro.org> References: <20230222020023.904232-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Pierrick Bouvier ctr_el0 access is privileged on this platform and fails as an illegal instruction. Windows does not offer a way to flush data cache from userspace, and only FlushInstructionCache is available in Windows API. The generic implementation of flush_idcache_range uses, __builtin___clear_cache, which already use the FlushInstructionCache function. So we rely on that. Signed-off-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-Id: <20230221153006.20300-2-pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson --- util/cacheflush.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/util/cacheflush.c b/util/cacheflush.c index 2c2c73e085..06c2333a60 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -121,8 +121,12 @@ static void sys_cache_info(int *isize, int *dsize) static bool have_coherent_icache; #endif -#if defined(__aarch64__) && !defined(CONFIG_DARWIN) -/* Apple does not expose CTR_EL0, so we must use system interfaces. */ +#if defined(__aarch64__) && !defined(CONFIG_DARWIN) && !defined(CONFIG_WIN32) +/* + * Apple does not expose CTR_EL0, so we must use system interfaces. + * Windows neither, but we use a generic implementation of flush_idcache_range + * in this case. + */ static uint64_t save_ctr_el0; static void arch_cache_info(int *isize, int *dsize) { @@ -225,7 +229,11 @@ static void __attribute__((constructor)) init_cache_info(void) /* Caches are coherent and do not require flushing; symbol inline. */ -#elif defined(__aarch64__) +#elif defined(__aarch64__) && !defined(CONFIG_WIN32) +/* + * For Windows, we use generic implementation of flush_idcache_range, that + * performs a call to FlushInstructionCache, through __builtin___clear_cache. + */ #ifdef CONFIG_DARWIN /* Apple does not expose CTR_EL0, so we must use system interfaces. */