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[95.127.39.43]) by smtp.gmail.com with ESMTPSA id z5-20020a5d4c85000000b002c71703876bsm504884wrs.14.2023.03.02.14.41.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 02 Mar 2023 14:41:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Bernhard Beschow Cc: John Snow , David Woodhouse , BALATON Zoltan , =?utf-8?q?Herv=C3=A9_Poussineau?= , qemu-ppc@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-block@nongnu.org Subject: [PATCH v3 02/18] hw/ide/piix: Allow using PIIX3-IDE as standalone PCI function Date: Thu, 2 Mar 2023 23:40:42 +0100 Message-Id: <20230302224058.43315-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230302224058.43315-1-philmd@linaro.org> References: <20230302224058.43315-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to allow Frankenstein uses such plugging a PIIX3 IDE function on a ICH9 chipset (which already exposes AHCI ports...) as: $ qemu-system-x86_64 -M q35 -device piix3-ide add a kludge to automatically wires the IDE IRQs on an ISA bus exposed by a PCI-to-ISA bridge (usually function #0). Restrict this kludge to the PIIX3. Reported-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé --- TODO: describe why this configuration is broken (multiple output IRQs wired to the same input IRQ can lead to various IRQ level changed in the iothread, thus missed by the vCPUs). --- hw/ide/piix.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index a36dac8469..7cb96ef67f 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -170,6 +170,18 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d); + if (!d->isa_irq[0] && !d->isa_irq[1] + && DEVICE_GET_CLASS(d)->user_creatable) { + /* kludge specific to TYPE_PIIX3_IDE */ + Object *isabus = object_resolve_path_type("", TYPE_ISA_BUS, NULL); + + if (!isabus) { + error_setg(errp, "Unable to find a single ISA bus"); + return; + } + d->isa_irq[0] = isa_bus_get_irq(ISA_BUS(isabus), 14); + d->isa_irq[1] = isa_bus_get_irq(ISA_BUS(isabus), 15); + } for (unsigned i = 0; i < ARRAY_SIZE(d->isa_irq); i++) { if (!pci_piix_init_bus(d, i, errp)) { return; @@ -202,6 +214,13 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_STORAGE_IDE; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable = false; + /* + * This function is part of a Super I/O chip and shouldn't be user + * creatable. However QEMU accepts impossible hardware setups such + * plugging a PIIX IDE function on a ICH ISA bridge. + * Keep this Frankenstein (ab)use working. + */ + dc->user_creatable = true; } static const TypeInfo piix3_ide_info = { @@ -225,6 +244,8 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_STORAGE_IDE; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable = false; + /* Reason: Part of a Super I/O chip */ + dc->user_creatable = false; } static const TypeInfo piix4_ide_info = {