| Message ID | 20230306015710.1868853-2-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Issue memory barriers for guest memory model | expand |
On 6/3/23 02:57, Richard Henderson wrote: > The virtio devices require proper memory ordering between > the vcpus and the iothreads. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/tcg-op.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 77658a88f0..75fdcdaac7 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -102,9 +102,13 @@ void tcg_gen_br(TCGLabel *l) void tcg_gen_mb(TCGBar mb_type) { - if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) { - tcg_gen_op1(INDEX_op_mb, mb_type); - } + /* + * It is tempting to elide the barrier in a single-threaded context + * (i.e. !(cflags & CF_PARALLEL)), however, even with a single cpu + * we have i/o threads running in parallel, and lack of memory order + * can result in e.g. virtio queue entries being read incorrectly. + */ + tcg_gen_op1(INDEX_op_mb, mb_type); } /* 32 bit ops */
The virtio devices require proper memory ordering between the vcpus and the iothreads. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/tcg-op.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)