From patchwork Tue Apr 11 01:05:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 672307 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:184:0:0:0:0 with SMTP id p4csp537151wrx; Mon, 10 Apr 2023 18:11:56 -0700 (PDT) X-Google-Smtp-Source: AKy350ZqX+AsekMsscPq09bbs8IaUkZweiKVf45FaBxHoss5MItuL6k9x+iRlmJqFY8F0fpfO/IF X-Received: by 2002:ac8:57c1:0:b0:3bf:c407:10ca with SMTP id w1-20020ac857c1000000b003bfc40710camr22484664qta.10.1681175516083; Mon, 10 Apr 2023 18:11:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1681175516; cv=none; d=google.com; s=arc-20160816; b=GpdYCx2olLrusn5S3m1g0Psjn5z5c6iXociVDzPuFBMtpBhfuhpF8tpp3PYEmuQ8fY P373yWnEzEPyUk1vEnljz1QLFrXrX/1mY16PKt3bcRQW/K8bJXQ8xqhXJKK+jBb4CVWe wHrEOZeMpxiucS+1HbN0/BAef8cd0T/U7lsiZjRhgqwzKGIpb6n8ld284Ad4h3JKGjvv no1Bc+5TqvavTk4/uAPKVHENo0+y+WZeNfWV4oijC7yV6G/YVEng28ilgA0zcDWlAR9A REUrwqQwdzSoWTm8BaP9Y3hd8u3aUON9ywj566V4XOA8ArJaY7xlAghOXC4dDyW+uEI+ ewmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4JSaZMhnEMUfPteRfFZgSSnL57XRI/bfHadrAPHwGBY=; b=hN9pOoJ8baAqkDmpSYIAmImkxWs7Ypzr892ygS62nQ9D3DtTfRQN0Xc+6xyDv3KuhR gHnDMADRmXooPEk/sga77h5qKfgXInOdyK8r/U/FVAM+1/5itLOruHUsJxRIujtCbkSg ZQvsVZWNtzONXfIXF9PDuEdBL5hgI8Y89/41tfBWIrN9MMLxbjXeNl0gvQvBz+wOGTlB VfLI2A5BMmGyDiOLrHm4ezFzRQ8T32q2pyRPEqaD/R2TJgttb37R/f/ByDjfPv9qfrj6 nykEXGBxWSY/1aMEj7yjFM2s1DbeEkQAwiTMpajxczOMZDPinGKztnf6q8AEC+PYO0TI MaQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="c/wmJO9N"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m8-20020ac85b08000000b003e398af5dcdsi7849639qtw.599.2023.04.10.18.11.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Apr 2023 18:11:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="c/wmJO9N"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pm2Wr-0005yb-3N; Mon, 10 Apr 2023 21:10:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pm2Wg-0005DC-Hp for qemu-devel@nongnu.org; Mon, 10 Apr 2023 21:10:26 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pm2WZ-0001ut-23 for qemu-devel@nongnu.org; Mon, 10 Apr 2023 21:10:26 -0400 Received: by mail-pj1-x1032.google.com with SMTP id q15-20020a17090a2dcf00b0023efab0e3bfso9277374pjm.3 for ; Mon, 10 Apr 2023 18:10:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1681175418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4JSaZMhnEMUfPteRfFZgSSnL57XRI/bfHadrAPHwGBY=; b=c/wmJO9NYa2Zku7HsqgaWupgKXM8Q+BkFSV9n/iVJClcdbuZ1IwT7dYhiD8rMD26lg RD+mG1FfIt4LjtujeTFh9XIGXbM1fXM4WreIjBIuhLHKZW6elCTE7es99vHYgjeJPyrf qiaPEEm3oRrygz4hFlebALgIck4ESykhRVhPdzeMN8O2QnR7BfoUA4heRMOghb8+LObN g70zY+3zlsUdvL5uyr8jUlHA+RT8Iaasntd9xvYvQxfHKoSQveH+c659VOIjuaiYVrA3 wye79RXPfH7oii1n/ga4BqjmiAw7JOssUhO94L/YwDrIZKtkjJUXXgDahBis1qUtsL7R f0rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681175418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4JSaZMhnEMUfPteRfFZgSSnL57XRI/bfHadrAPHwGBY=; b=NEgOb1xMtkEPnTB1DCVW8N6rRTHFixDS14hQ5hUmG01gY4h8vZrNVSu/mPhUVBgBX9 2jcqSuqZZ/Pj9ClB1kJPHGVJq4cKiabItlH8vDYSdqzJTyNN3I+JXIeXyjQVevwAeqHw FxKeKOhHOeeL3teN2FdBY3jyBh56M3npnazfp/xNfujXm1lrlsnVV43YwoKFxHz+0Pm0 +3O3nDY0MY0g1RZ1BIVNWStCLHZCbgvewzzwNx6SD81B71r0QQzKHCPrdY4HZstlchRW NyxqauTafbM9CuFgIrH+BZ3MChrWsS2QXWBcbBSZ01CTirHdfPOTW552P2aZKCB/QRe8 cGTg== X-Gm-Message-State: AAQBX9el7e6m+83bUnP3hwXiM0t7f7rhHWTqXf7sPL9lifWMHO22HGRm kFv+k+UAoi8QMawU+iykbZearp07PFalkw+wWhZwaw== X-Received: by 2002:a17:903:846:b0:1a5:167e:f47d with SMTP id ks6-20020a170903084600b001a5167ef47dmr11136493plb.34.1681175418213; Mon, 10 Apr 2023 18:10:18 -0700 (PDT) Received: from stoup.WiFi.IPv4InfoBelow (h146.238.133.40.static.ip.windstream.net. [40.133.238.146]) by smtp.gmail.com with ESMTPSA id p12-20020a1709028a8c00b001a63deeb5e2sm2652130plo.92.2023.04.10.18.10.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 18:10:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 50/54] tcg/ppc: Adjust constraints on qemu_ld/st Date: Mon, 10 Apr 2023 18:05:08 -0700 Message-Id: <20230411010512.5375-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230411010512.5375-1-richard.henderson@linaro.org> References: <20230411010512.5375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza --- tcg/ppc/tcg-target-con-set.h | 11 ++++------- tcg/ppc/tcg-target-con-str.h | 2 -- tcg/ppc/tcg-target.c.inc | 32 ++++++++++---------------------- 3 files changed, 14 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target-con-set.h b/tcg/ppc/tcg-target-con-set.h index a1a345883d..f206b29205 100644 --- a/tcg/ppc/tcg-target-con-set.h +++ b/tcg/ppc/tcg-target-con-set.h @@ -12,18 +12,15 @@ C_O0_I1(r) C_O0_I2(r, r) C_O0_I2(r, ri) -C_O0_I2(S, S) C_O0_I2(v, r) -C_O0_I3(S, S, S) +C_O0_I3(r, r, r) C_O0_I4(r, r, ri, ri) -C_O0_I4(S, S, S, S) -C_O1_I1(r, L) +C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I1(v, r) C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, rZ) -C_O1_I2(r, L, L) C_O1_I2(r, rI, ri) C_O1_I2(r, rI, rT) C_O1_I2(r, r, r) @@ -36,7 +33,7 @@ C_O1_I2(v, v, v) C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, rZ, rZ) C_O1_I4(r, r, r, ri, ri) -C_O2_I1(L, L, L) -C_O2_I2(L, L, L, L) +C_O2_I1(r, r, r) +C_O2_I2(r, r, r, r) C_O2_I4(r, r, rI, rZM, r, r) C_O2_I4(r, r, r, r, rI, rZM) diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h index 298ca20d5b..f3bf030bc3 100644 --- a/tcg/ppc/tcg-target-con-str.h +++ b/tcg/ppc/tcg-target-con-str.h @@ -14,8 +14,6 @@ REGS('A', 1u << TCG_REG_R3) REGS('B', 1u << TCG_REG_R4) REGS('C', 1u << TCG_REG_R5) REGS('D', 1u << TCG_REG_R6) -REGS('L', ALL_QLOAD_REGS) -REGS('S', ALL_QSTORE_REGS) /* * Define constraint letters for constants: diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 613cd73583..e94f3131a3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -93,18 +93,6 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull -#ifdef CONFIG_SOFTMMU -#define ALL_QLOAD_REGS \ - (ALL_GENERAL_REGS & \ - ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) -#define ALL_QSTORE_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ - (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) -#else -#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) -#define ALL_QSTORE_REGS ALL_QLOAD_REGS -#endif - TCGPowerISA have_isa; static bool have_isel; bool have_altivec; @@ -3791,23 +3779,23 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_qemu_ld_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? C_O1_I1(r, L) - : C_O1_I2(r, L, L)); + ? C_O1_I1(r, r) + : C_O1_I2(r, r, r)); case INDEX_op_qemu_st_i32: return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 - ? C_O0_I2(S, S) - : C_O0_I3(S, S, S)); + ? C_O0_I2(r, r) + : C_O0_I3(r, r, r)); case INDEX_op_qemu_ld_i64: - return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) - : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L) - : C_O2_I2(L, L, L, L)); + return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) + : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, r) + : C_O2_I2(r, r, r, r)); case INDEX_op_qemu_st_i64: - return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S) - : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S) - : C_O0_I4(S, S, S, S)); + return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) + : TARGET_LONG_BITS == 32 ? C_O0_I3(r, r, r) + : C_O0_I4(r, r, r, r)); case INDEX_op_add_vec: case INDEX_op_sub_vec: