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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id l19-20020a170902d35300b0019309be03e7sm218762plk.66.2023.05.04.18.07.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 May 2023 18:07:07 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis , Weiwei Li , Daniel Henrique Barboza Subject: [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Date: Fri, 5 May 2023 11:02:19 +1000 Message-Id: <20230505010241.21812-68-alistair.francis@wdc.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com> References: <20230505010241.21812-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Weiwei Li Tested-by: Daniel Henrique Barboza Message-Id: <20230325105429.1142530-12-richard.henderson@linaro.org> Message-Id: <20230412114333.118895-12-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 6 ++++-- target/riscv/cpu_helper.c | 2 +- target/riscv/op_helper.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b55152a7dc..7b63c0f1b6 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -27,13 +27,15 @@ * - S 0b001 * - S+SUM 0b010 * - M 0b011 - * - HLV/HLVX/HSV adds 0b100 + * - U+2STAGE 0b100 + * - S+2STAGE 0b101 + * - S+SUM+2STAGE 0b110 */ #define MMUIdx_U 0 #define MMUIdx_S 1 #define MMUIdx_S_SUM 2 #define MMUIdx_M 3 -#define MMU_HYP_ACCESS_BIT (1 << 2) +#define MMU_2STAGE_BIT (1 << 2) /* share data between vector helpers and decode code */ FIELD(VDATA, VM, 0, 1) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index abf275d2c6..291a1acbf7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -593,7 +593,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) bool riscv_cpu_two_stage_lookup(int mmu_idx) { - return mmu_idx & MMU_HYP_ACCESS_BIT; + return mmu_idx & MMU_2STAGE_BIT; } int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 7f83395370..6122f5fbe5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -437,7 +437,7 @@ static int check_access_hlsv(CPURISCVState *env, bool x, uintptr_t ra) riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, ra); } - return cpu_mmu_index(env, x) | MMU_HYP_ACCESS_BIT; + return cpu_mmu_index(env, x) | MMU_2STAGE_BIT; } target_ulong helper_hyp_hlv_bu(CPURISCVState *env, target_ulong addr)