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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id b5-20020adff905000000b0030aedb8156esm8998995wrr.102.2023.06.11.01.59.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/26] target/arm/tcg: Expose some iwmmxt methods in 'translate.h' Date: Sun, 11 Jun 2023 10:58:27 +0200 Message-Id: <20230611085846.21415-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose a few methods and variables before extracting iwmmxt code from translate.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/translate.h | 6 ++++++ target/arm/tcg/translate.c | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d1cacff0b2..3d7c55d3b6 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -165,6 +165,7 @@ typedef struct DisasCompare { } DisasCompare; /* Share the TCG temporaries common between 32 and 64 bit modes. */ +extern TCGv_i32 cpu_R[16]; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; @@ -298,6 +299,11 @@ static inline int curr_insn_len(DisasContext *s) /* CPU state was modified dynamically; no need to exit, but do not chain. */ #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 +/* These are TCG temporaries used only by the legacy iwMMXt decoder */ +extern TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn); +int disas_dsp_insn(DisasContext *s, uint32_t insn); + #ifdef TARGET_AARCH64 void a64_translate_init(void); void gen_a64_update_pc(DisasContext *s, target_long diff); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3238463f13..aaa479521e 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -45,9 +45,9 @@ #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) /* These are TCG temporaries used only by the legacy iwMMXt decoder */ -static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ -static TCGv_i32 cpu_R[16]; +TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; @@ -1490,7 +1490,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest) * Disassemble an iwMMXt instruction. * Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) { int rd, wrd; int rdhi, rdlo, rd0, rd1, i; @@ -2509,7 +2509,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) * Disassemble an XScale DSP instruction. * Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_dsp_insn(DisasContext *s, uint32_t insn) +int disas_dsp_insn(DisasContext *s, uint32_t insn) { int acc, rd0, rd1, rdhi, rdlo; TCGv_i32 tmp, tmp2;