From patchwork Mon Jul 31 14:15:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 708409 Delivered-To: patch@linaro.org Received: by 2002:a5d:6787:0:b0:317:2194:b2bc with SMTP id v7csp2330024wru; Mon, 31 Jul 2023 07:16:13 -0700 (PDT) X-Google-Smtp-Source: APBJJlHYTmqNu2Z2dR5kbGUMLH0W74gxmkaRV1Cpo48p2l5T6DZ9M1x0DcnnQ5Jkwlimt0wY+zFy X-Received: by 2002:a1f:3d07:0:b0:486:3f48:be7f with SMTP id k7-20020a1f3d07000000b004863f48be7fmr3728354vka.6.1690812973667; Mon, 31 Jul 2023 07:16:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1690812973; cv=none; d=google.com; s=arc-20160816; b=bT57b35yS8ttoLFcW0EFFjAS2m+uQOeSHb0DdvPYPPG/BgPJb1jnRA5+ymAzSR2ihI k6SRser2BvQTpYq/DMSNRfwXnGtkXwe1ST97BF7KUF442GpYuHy250iD24lM7w0RvZ00 9k5P6QqHISgPa/2Jd3YSPDPdENAxlmVGV9siMa3GvNq2KZVTRJJ9a5+XIh+tkjpk/unn k0DlPFbmcE1JC4mrb5FoGFl+ZKkhyA327gMjbkLCPWD+jB0XfJeLkZynZdGvowQ+xyfI LV0L3eXkhkmTjTUX/R9x0sfNmSSFQR3q70QIKaRyOB+sV/RMXVYZhwzFn0fanKJi6O0I ARTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=STtOVksr63dEkZ6wAYpplxRzfdJwT/NJYMmDJPe/tsc=; fh=bFDrUYhlTVi/QyetgXx/byg2+yO/22Hp9SjwoefyKLk=; b=x7RgHpjnNuTKD6dRgVJAzmL70hmqk5G+V0jAjK0K10XHVHMBVvmkyHrf7hrSaxTy3z hQBRqG3ywep9oMMo8Wk5FimGDPbU/sKH2nvY62wNw347LL+2lvFnzXDNmVn1u5MXWcXS aYfVVIYTAEzVPV7DNM16dl3BSm4r1A0CKoZY1ay5O+sxlw2QSdgTWwogXCIJCC481Yjp JE8u6xjCx3PuOo3hwOPVsQl7NTHPlpuonaU+LvJP01odB2tKwz2xZcZbt4SZW1I8Vm7v 79pYwObbcnjV0xZIB0v05Wu0yDRXA6lQsehXV8FKye2dEAJ5XE9NU/iumK1blazJ1SUr hEDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJcIdCam; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h8-20020a056102208800b004450872d17dsi786421vsr.396.2023.07.31.07.16.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 31 Jul 2023 07:16:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RJcIdCam; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qQTgW-0005a1-0o; Mon, 31 Jul 2023 10:15:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qQTgS-0005WZ-KE for qemu-devel@nongnu.org; Mon, 31 Jul 2023 10:15:40 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qQTgQ-0007eb-CQ for qemu-devel@nongnu.org; Mon, 31 Jul 2023 10:15:40 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-3fe2048c910so9789015e9.1 for ; Mon, 31 Jul 2023 07:15:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690812936; x=1691417736; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=STtOVksr63dEkZ6wAYpplxRzfdJwT/NJYMmDJPe/tsc=; b=RJcIdCamjcgBEAeVlxYWD5La8/Z/AbzTtdhYk+pkGqMUv0uURpf3huWY/cBt0RXN7p 2EKT0ClB4sWqzqwji4pluVQFEk8qmPbGyWl8oz9QDijka+vowSzIuKPFTGTd8AjEFbjN zNsAnjVbFc9fRY7hI+mkQFbNoF/vBZbpU7ogrv0tHaQ8b9M5xN/s8fNvV0VWOizi605L Qf0ucEO1WK5Xow24bDOaaX+wooSnQ4rtVtg/7VsgVGMA7ygTjrqCegL02nB7hn0N31XY XUjNRpN4p0xt7qgZ1U5ruOGvVduLJtnSTzbmBdLU2RM17L4UN82jpmosJjTKw5v+tWOZ SU/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690812936; x=1691417736; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=STtOVksr63dEkZ6wAYpplxRzfdJwT/NJYMmDJPe/tsc=; b=SG/inmGSQWxwfaYiyzjcLHh6PiINhSRcly5/hSBZSpuTyAEkRizUWbJ8/m+HsB/X3w 8CFqxJPmpVvHa8PHe3T6y1bOHlm8ih1ZC43Q3JIAojPjNLYAmW+RTYQ0WGf3gV3JVChS Uo5qIPW4EbHxYzLFL2Y584Y01TohcLSs6KTgNJL68hkEYpSUlRgP5GWJ+2xkraW3lFnp YlZLLG7ctBcFm1PQYF2f0lHKp3i6NJzfZOPrm54oVicRpOeO8Z4dOiwgk/K/gJI3QQzJ BEbH8AliNJKqAyZQf2JD5FgZyn04Ou8AOP28CPrnF6Mhc+pkPCtpmyDnbyJLnM7uXzbz rPpw== X-Gm-Message-State: ABy/qLYcjaqiFdN+018IGBOUnBx6HfVx+QjwE8A1bovKNYZRyeAzQZQ1 jYq+aV+xaQYmv/k6eGwwW4XqN1hFckrZp0mJsx0= X-Received: by 2002:a05:600c:2a4e:b0:3f9:b30f:a013 with SMTP id x14-20020a05600c2a4e00b003f9b30fa013mr76243wme.6.1690812936651; Mon, 31 Jul 2023 07:15:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id z15-20020a05600c114f00b003fbb5506e54sm11450675wmz.29.2023.07.31.07.15.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 07:15:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 3/6] target/arm: Avoid writing to constant TCGv in trans_CSEL() Date: Mon, 31 Jul 2023 15:15:30 +0100 Message-Id: <20230731141533.3303894-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230731141533.3303894-1-peter.maydell@linaro.org> References: <20230731141533.3303894-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 0b188ea05acb5 we changed the implementation of trans_CSEL() to use tcg_constant_i32(). However, this change was incorrect, because the implementation of the function sets up the TCGv_i32 rn and rm to be either zero or else a TCG temp created in load_reg(), and these TCG temps are then in both cases written to by the emitted TCG ops. The result is that we hit a TCG assertion: qemu-system-arm: ../../tcg/tcg.c:4455: tcg_reg_alloc_mov: Assertion `!temp_readonly(ots)' failed. (or on a non-debug build, just produce a garbage result) Adjust the code so that rn and rm are always writeable temporaries whether the instruction is using the special case "0" or a normal register as input. Cc: qemu-stable@nongnu.org Fixes: 0b188ea05acb5 ("target/arm: Use tcg_constant in trans_CSEL") Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20230727103906.2641264-1-peter.maydell@linaro.org --- target/arm/tcg/translate.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 13c88ba1b9f..b71ac2d0d53 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -8799,7 +8799,7 @@ static bool trans_IT(DisasContext *s, arg_IT *a) /* v8.1M CSEL/CSINC/CSNEG/CSINV */ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) { - TCGv_i32 rn, rm, zero; + TCGv_i32 rn, rm; DisasCompare c; if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { @@ -8817,16 +8817,17 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) } /* In this insn input reg fields of 0b1111 mean "zero", not "PC" */ - zero = tcg_constant_i32(0); + rn = tcg_temp_new_i32(); + rm = tcg_temp_new_i32(); if (a->rn == 15) { - rn = zero; + tcg_gen_movi_i32(rn, 0); } else { - rn = load_reg(s, a->rn); + load_reg_var(s, rn, a->rn); } if (a->rm == 15) { - rm = zero; + tcg_gen_movi_i32(rm, 0); } else { - rm = load_reg(s, a->rm); + load_reg_var(s, rm, a->rm); } switch (a->op) { @@ -8846,7 +8847,7 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) } arm_test_cc(&c, a->fcond); - tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm); + tcg_gen_movcond_i32(c.cond, rn, c.value, tcg_constant_i32(0), rn, rm); store_reg(s, a->rd, rn); return true;