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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id u1-20020a17090282c100b001bbf7fd354csm2185568plz.213.2023.08.04.15.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 15:00:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Nathan Egge , Daniel Henrique Barboza Subject: [PATCH v9 24/24] linux-user/elfload: Set V in ELF_HWCAP for RISC-V Date: Fri, 4 Aug 2023 15:00:32 -0700 Message-Id: <20230804220032.295411-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804220032.295411-1-richard.henderson@linaro.org> References: <20230804220032.295411-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Nathan Egge Set V bit for hwcap if misa is set. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1793 Signed-off-by: Nathan Egge Reviewed-by: Daniel Henrique Barboza Tested-by: Daniel Henrique Barboza Message-Id: <20230803131424.40744-1-negge@xiph.org> Signed-off-by: Richard Henderson --- linux-user/elfload.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 51591a1d94..c9e176a9f6 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1710,7 +1710,8 @@ static uint32_t get_elf_hwcap(void) #define MISA_BIT(EXT) (1 << (EXT - 'A')) RISCVCPU *cpu = RISCV_CPU(thread_cpu); uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A') - | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C'); + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C') + | MISA_BIT('V'); return cpu->env.misa_ext & mask; #undef MISA_BIT