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([2602:47:d483:7301:e773:351d:2db2:8a8a]) by smtp.gmail.com with ESMTPSA id gk18-20020a17090b119200b00263ba6a248bsm5723840pjb.1.2023.08.11.14.40.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Aug 2023 14:40:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 08/11] target/arm: Implement RMR_EL3 for neoverse-v1 Date: Fri, 11 Aug 2023 14:40:28 -0700 Message-Id: <20230811214031.171020-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230811214031.171020-1-richard.henderson@linaro.org> References: <20230811214031.171020-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b0cac05be6..0054bb6dfa 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -573,6 +573,18 @@ static const ARMCPRegInfo neoverse_v1_cp_reginfo[] = { .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, }; +/* + * TODO: For a write with bit 1 set, do something with arm_reset_cpu(). + * In the meantime, "the bit is strictly a request", so we are in spec + * just ignoring writes. + */ +static const ARMCPRegInfo rmr_reginfo = { + .name = "RMR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 2, + .access = PL3_RW, .type = ARM_CP_CONST, + .resetvalue = 1, /* [31:2] RES0, [1] reset 0, [0] RES1 */ +}; + static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) { /* @@ -581,6 +593,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) */ define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); + define_one_arm_cp_reg(cpu, &rmr_reginfo); } static void aarch64_neoverse_n1_initfn(Object *obj)