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[176.182.122.208]) by smtp.gmail.com with ESMTPSA id i14-20020a5d630e000000b0031980783d78sm12415396wru.54.2023.08.21.06.00.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 21 Aug 2023 06:00:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Song Gao , Jiajie Chen , Xiaojuan Yang , Huacai Chen , Richard Henderson Subject: [PATCH v3 7/8] target/loongarch: Add new object class for loongarch32 cpus Date: Mon, 21 Aug 2023 14:59:58 +0200 Message-ID: <20230821125959.28666-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230821125959.28666-1-philmd@linaro.org> References: <20230821125959.28666-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jiajie Chen Add object class stub for future loongarch32 cpus. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao Message-ID: <20230817093121.1053890-3-gaosong@loongson.cn> [Rebased on TYPE_LOONGARCH64_CPU introduction] Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/cpu.h | 1 + target/loongarch/cpu.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 3235ad081f..b8af491041 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -382,6 +382,7 @@ struct ArchCPU { }; #define TYPE_LOONGARCH_CPU "loongarch-cpu" +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" #define TYPE_LOONGARCH64_CPU "loongarch64-cpu" OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 6384bda1bd..556419f159 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -726,6 +726,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) #endif } +static void loongarch32_cpu_class_init(ObjectClass *c, void *data) +{ +} + static gchar *loongarch64_gdb_arch_name(CPUState *cs) { return g_strdup("loongarch64"); @@ -758,6 +762,13 @@ static const TypeInfo loongarch_cpu_type_infos[] = { .class_size = sizeof(LoongArchCPUClass), .class_init = loongarch_cpu_class_init, }, + { + .name = TYPE_LOONGARCH32_CPU, + .parent = TYPE_LOONGARCH_CPU, + + .abstract = true, + .class_init = loongarch32_cpu_class_init, + }, { .name = TYPE_LOONGARCH64_CPU, .parent = TYPE_LOONGARCH_CPU,