[PULL,35/35] target/arm: Fix 64-bit SSRA

Message ID	20230824092836.2239644-36-peter.maydell@linaro.org
State	Accepted
Commit	cd1e4db73646006039f25879af3bff55b2295ff3
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 35/35] target/arm: Fix 64-bit SSRA Date: Thu, 24 Aug 2023 10:28:36 +0100 Message-Id: <20230824092836.2239644-36-peter.maydell@linaro.org> In-Reply-To: <20230824092836.2239644-1-peter.maydell@linaro.org> References: <20230824092836.2239644-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/35] hw/gpio/nrf51: implement DETECT signal \| expand [PULL,01/35] hw/gpio/nrf51: implement DETECT signal [PULL,02/35] qtest: factor out qtest_install_gpio_out_intercept [PULL,03/35] qtest: implement named interception of out-GPIO [PULL,04/35] qtest: bail from irq_intercept_in if name is specified [PULL,05/35] qtest: irq_intercept_[out/in]: return FAIL if no intercepts are installed [PULL,06/35] qtest: microbit-test: add tests for nRF51 DETECT [PULL,07/35] kvm: Introduce kvm_arch_get_default_type hook [PULL,08/35] accel/kvm: Specify default IPA size for arm64 [PULL,09/35] mips: Report an error when KVM_VM_MIPS_VZ is unavailable [PULL,10/35] accel/kvm: Use negative KVM type for error propagation [PULL,11/35] accel/kvm: Free as when an error occurred [PULL,12/35] accel/kvm: Make kvm_dirty_ring_reaper_init() void [PULL,13/35] target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault [PULL,14/35] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults [PULL,15/35] target/arm/ptw: Set s1ns bit in fault info more consistently [PULL,16/35] target/arm/ptw: Pass ptw into get_phys_addr_pmsa() and get_phys_addr_disabled() [PULL,17/35] target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled() [PULL,18/35] target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate() [PULL,19/35] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate() [PULL,20/35] target/arm/ptw: Only fold in NSTable bit effects in Secure state [PULL,21/35] target/arm/ptw: Remove last uses of ptw->in_secure [PULL,22/35] target/arm/ptw: Remove S1Translate::in_secure [PULL,23/35] target/arm/ptw: Drop S1Translate::out_secure [PULL,24/35] target/arm/ptw: Set attributes correctly for MMU disabled data accesses [PULL,25/35] target/arm/ptw: Check for block descriptors at invalid levels [PULL,26/35] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw [PULL,27/35] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types [PULL,28/35] target/arm/ptw: Load stage-2 tables from realm physical space [PULL,29/35] target/arm/helper: Fix tlbmask and tlbbits for TLBI VAE2 [PULL,30/35] target/arm: Skip granule protection checks for AT instructions [PULL,31/35] target/arm: Pass security space rather than flag for AT instructions [PULL,32/35] target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for AT instructions [PULL,33/35] target/arm/helper: Implement CNTHCTL_EL2.CNT[VP]MASK [PULL,34/35] target/arm: Fix SME ST1Q [PULL,35/35] target/arm: Fix 64-bit SSRA

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20230824092836.2239644-36-peter.maydell@linaro.org

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Accepted

Commit

cd1e4db73646006039f25879af3bff55b2295ff3

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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 35/35] target/arm: Fix 64-bit SSRA
Date: Thu, 24 Aug 2023 10:28:36 +0100
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Series

[PULL,01/35] hw/gpio/nrf51: implement DETECT signal | expand

Commit Message

Peter Maydell Aug. 24, 2023, 9:28 a.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

Typo applied byte-wise shift instead of double-word shift.

Cc: qemu-stable@nongnu.org
Fixes: 631e565450c ("target/arm: Create gen_gvec_[us]sra")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1737
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20230821022025.397682-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index b71ac2d0d53..39541ecdf0a 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -3053,7 +3053,7 @@  void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
           .vece = MO_32 },
         { .fni8 = gen_ssra64_i64,
           .fniv = gen_ssra_vec,
-          .fno = gen_helper_gvec_ssra_b,
+          .fno = gen_helper_gvec_ssra_d,
           .prefer_i64 = TCG_TARGET_REG_BITS == 64,
           .opt_opc = vecop_list,
           .load_dest = true,

[PULL,35/35] target/arm: Fix 64-bit SSRA

Commit Message

Patch