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[212.78.193.212]) by smtp.gmail.com with ESMTPSA id y16-20020a170906559000b0099b7276235esm6699286ejp.93.2023.09.18.09.03.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 18 Sep 2023 09:03:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Laurent Vivier , Paolo Bonzini , Max Filippov , David Hildenbrand , Peter Xu , Anton Johansson , Peter Maydell , kvm@vger.kernel.org, Marek Vasut , David Gibson , Brian Cain , Yoshinori Sato , "Edgar E . Iglesias" , Claudio Fontana , Daniel Henrique Barboza , Artyom Tarasenko , Marcelo Tosatti , qemu-ppc@nongnu.org, Liu Zhiwei , Aurelien Jarno , Ilya Leoshkevich , Daniel Henrique Barboza , Bastian Koppelmann , =?utf-8?q?C=C3=A9dric_?= =?utf-8?q?Le_Goater?= , Alistair Francis , Alessandro Di Federico , Song Gao , Marcel Apfelbaum , Chris Wulff , "Michael S. Tsirkin" , Alistair Francis , Fabiano Rosas , qemu-s390x@nongnu.org, Yanan Wang , Luc Michel , Weiwei Li , Bin Meng , Stafford Horne , Xiaojuan Yang , "Daniel P . Berrange" , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Jiaxun Yang , Richard Henderson , Aleksandar Rikalo , Bernhard Beschow , Mark Cave-Ayland , qemu-riscv@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Nicholas Piggin , Greg Kurz , Michael Rolnik , Eduardo Habkost , Markus Armbruster , Palmer Dabbelt Subject: [PATCH 02/22] hw/intc/apic: Pass CPU using QOM link property Date: Mon, 18 Sep 2023 18:02:35 +0200 Message-ID: <20230918160257.30127-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230918160257.30127-1-philmd@linaro.org> References: <20230918160257.30127-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QOM objects shouldn't access each other internals fields except using the QOM API. Declare the 'cpu' and 'base-addr' properties, set them using object_property_set_link() and qdev_prop_set_uint32() respectively. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Igor Mammedov --- hw/intc/apic_common.c | 2 ++ target/i386/cpu-sysemu.c | 11 ++++++----- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 68ad30e2f5..e28f7402ab 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -394,6 +394,8 @@ static Property apic_properties_common[] = { true), DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, false), + DEFINE_PROP_LINK("cpu", APICCommonState, cpu, TYPE_X86_CPU, X86CPU *), + DEFINE_PROP_UINT32("base-addr", APICCommonState, apicbase, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 6a164d3769..6edfb7e2af 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -269,7 +269,6 @@ APICCommonClass *apic_get_class(Error **errp) void x86_cpu_apic_create(X86CPU *cpu, Error **errp) { - APICCommonState *apic; APICCommonClass *apic_class = apic_get_class(errp); assert(apic_class); @@ -279,11 +278,13 @@ void x86_cpu_apic_create(X86CPU *cpu, Error **errp) OBJECT(cpu->apic_state)); object_unref(OBJECT(cpu->apic_state)); + if (!object_property_set_link(OBJECT(cpu->apic_state), "cpu", + OBJECT(cpu), errp)) { + return; + } qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id); - /* TODO: convert to link<> */ - apic = APIC_COMMON(cpu->apic_state); - apic->cpu = cpu; - apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE; + qdev_prop_set_uint32(cpu->apic_state, "base-addr", + APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE); } void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)