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[176.131.222.246]) by smtp.gmail.com with ESMTPSA id u19-20020a7bc053000000b003fefaf299b6sm698061wmc.38.2023.10.03.01.27.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 03 Oct 2023 01:27:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , Marcel Apfelbaum , Markus Armbruster , Richard Henderson , Peter Xu , Jason Wang , "Michael S. Tsirkin" , Eduardo Habkost , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/5] hw/i386/apic: Simplify apic_get_class() Date: Tue, 3 Oct 2023 10:27:26 +0200 Message-ID: <20231003082728.83496-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231003082728.83496-1-philmd@linaro.org> References: <20231003082728.83496-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12d; envelope-from=philmd@linaro.org; helo=mail-lf1-x12d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than apic_get_class() can not fail, remove its Error** parameter. It can't return NULL neither, so simplify x86_cpu_apic_create(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Xu --- include/hw/i386/apic_internal.h | 2 +- hw/i386/amd_iommu.c | 2 +- hw/i386/intel_iommu.c | 4 ++-- target/i386/cpu-sysemu.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_internal.h index 5f2ba24bfc..e61ad04769 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -225,6 +225,6 @@ static inline int apic_get_bit(uint32_t *tab, int index) return !!(tab[i] & mask); } -APICCommonClass *apic_get_class(Error **errp); +APICCommonClass *apic_get_class(void); #endif /* QEMU_APIC_INTERNAL_H */ diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index c98a3c6e11..0a95025ab7 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1368,7 +1368,7 @@ static MemTxResult amdvi_mem_ir_write(void *opaque, hwaddr addr, return MEMTX_ERROR; } - apic_get_class(NULL)->send_msi(&to); + apic_get_class()->send_msi(&to); trace_amdvi_mem_ir_write(to.address, to.data); return MEMTX_OK; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 2c832ab68b..dffe3583bd 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -397,7 +397,7 @@ static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg, trace_vtd_irq_generate(msi.address, msi.data); - apic_get_class(NULL)->send_msi(&msi); + apic_get_class()->send_msi(&msi); } /* Generate a fault event to software via MSI if conditions are met. @@ -3554,7 +3554,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr, return MEMTX_ERROR; } - apic_get_class(NULL)->send_msi(&to); + apic_get_class()->send_msi(&to); return MEMTX_OK; } diff --git a/target/i386/cpu-sysemu.c b/target/i386/cpu-sysemu.c index 6a228c9178..9038c65267 100644 --- a/target/i386/cpu-sysemu.c +++ b/target/i386/cpu-sysemu.c @@ -247,7 +247,7 @@ void x86_cpu_machine_reset_cb(void *opaque) cpu_reset(CPU(cpu)); } -APICCommonClass *apic_get_class(Error **errp) +APICCommonClass *apic_get_class(void) { const char *apic_type = "apic"; @@ -266,7 +266,7 @@ APICCommonClass *apic_get_class(Error **errp) void x86_cpu_apic_create(X86CPU *cpu, Error **errp) { APICCommonState *apic; - APICCommonClass *apic_class = apic_get_class(errp); + APICCommonClass *apic_class = apic_get_class(); cpu->apic_state = DEVICE(object_new_with_class(OBJECT_CLASS(apic_class))); object_property_add_child(OBJECT(cpu), "lapic",