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[209.51.188.17]) by mx.google.com with ESMTPS id j1-20020a37ef01000000b00767dfe07ec4si1177389qkk.164.2023.10.13.07.04.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2023 07:04:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wp7IVVd0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrImG-00039N-Dj; Fri, 13 Oct 2023 10:04:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrIkR-0007aL-Cc for qemu-devel@nongnu.org; Fri, 13 Oct 2023 10:02:40 -0400 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrIkJ-0002Lz-M8 for qemu-devel@nongnu.org; Fri, 13 Oct 2023 10:02:38 -0400 Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-9be1ee3dc86so10274266b.1 for ; Fri, 13 Oct 2023 07:02:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697205750; x=1697810550; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gkqit7if0np+hOPuR/lmFr1Vsbe3YApoPUZEdcDy8j8=; b=wp7IVVd0MoQDS/YwweUZ19//bP0+yjaq7MxBRZeyxSBAZhSHH1eSl8XCnISKSLwHP8 ziYpQICPoCm4+jZupLd16UsLPCM64+yNa2VfSrhx+jpYVsn/iHON158ogGMrrR6SaOQT aKOEL3hP81p3e8O1bRmVQ2CgfaZ5SIWsoRQCeRt7kTSoyP0UsNlOQLFLDfdsN7Sd8Ya1 KVi1tJkX/+x6C3COxb8Loy0wQmh2D8ApkfnqgmrYpu4E3SQMJC5vt5qFE2Al/VKxtXfO zpG8ChYQgndeuzmIANiW0fveHBo/PgGXs9iMjQYK5DtSQQsyxKuqhQW0ei/pRCjGxJs6 AAnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697205750; x=1697810550; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gkqit7if0np+hOPuR/lmFr1Vsbe3YApoPUZEdcDy8j8=; b=VQrrBJqgekOoZG4vd0Xb5A6Ya6ZrguRd9USbIqafb2WYw+X8YFZEWpcUdnzRzXkl9w 8kp0ppXrAl7Nb1WFpFvFqamFaeSvVpzso5fB3+1LZ0Sk+NkqSPdl0SV8/lC3bdNyQtFH zo6yNtKtpeaIu3y5+/Vk4kYGbaH7z9K9zsA9GKPb546oJrobS5gpJ3rYXBorXsv6K3sN o04dkiDoiPnf4jFsbEscYFpIqIdDRbj0j/JjOMuDf0rQu0Mv88pcvR9FeNmk3teuschl C2UZqrhx/DgqhN/dgtzcnG+wgbBNl7yIfZu2g1cawLy5M51cH9TF94XCXHCaSNKiBXvh zAQw== X-Gm-Message-State: AOJu0YyOU33uJKI2xWdylLo6hzAPeY+tx6pzcF0ate3YSL0mw0n28Oih kmiC5xcdU5WEKb3xTu+fXt16A9mDHcPr6hsb4S0= X-Received: by 2002:a17:907:9282:b0:9bd:bbc1:1c65 with SMTP id bw2-20020a170907928200b009bdbbc11c65mr1241200ejc.13.1697205749739; Fri, 13 Oct 2023 07:02:29 -0700 (PDT) Received: from m1x-phil.lan ([176.172.118.168]) by smtp.gmail.com with ESMTPSA id st12-20020a170907c08c00b009b9f87b34b6sm11026896ejc.189.2023.10.13.07.02.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 13 Oct 2023 07:02:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Xiaojuan Yang , "Michael S. Tsirkin" , qemu-ppc@nongnu.org, Aleksandar Rikalo , David Hildenbrand , qemu-s390x@nongnu.org, "Edgar E. Iglesias" , Jiaxun Yang , Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Stafford Horne , Alistair Francis , Yanan Wang , Max Filippov , Artyom Tarasenko , Marcel Apfelbaum , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Laurent Vivier , Aurelien Jarno , qemu-riscv@nongnu.org, Palmer Dabbelt , Yoshinori Sato , Bastian Koppelmann , Bin Meng , Daniel Henrique Barboza , Mark Cave-Ayland , Weiwei Li , Daniel Henrique Barboza , Nicholas Piggin , qemu-arm@nongnu.org, Liu Zhiwei , Marek Vasut , Laurent Vivier , Peter Maydell , Brian Cain , Thomas Huth , Chris Wulff , Sergio Lopez , Richard Henderson , Ilya Leoshkevich , Michael Rolnik Subject: [PATCH v2 07/16] target/hexagon: Declare QOM definitions in 'cpu-qom.h' Date: Fri, 13 Oct 2023 16:01:06 +0200 Message-ID: <20231013140116.255-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013140116.255-1-philmd@linaro.org> References: <20231013140116.255-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Brian Cain --- target/hexagon/cpu-qom.h | 28 ++++++++++++++++++++++++++++ target/hexagon/cpu.h | 15 +-------------- 2 files changed, 29 insertions(+), 14 deletions(-) create mode 100644 target/hexagon/cpu-qom.h diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h new file mode 100644 index 0000000000..f02df7ee6f --- /dev/null +++ b/target/hexagon/cpu-qom.h @@ -0,0 +1,28 @@ +/* + * QEMU Hexagon CPU QOM header (target agnostic) + * + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_HEXAGON_CPU_QOM_H +#define QEMU_HEXAGON_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_HEXAGON_CPU "hexagon-cpu" + +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU +#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) + +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") + +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) + +#endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 035ac4fb6d..7d16083c6a 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -20,11 +20,10 @@ #include "fpu/softfloat-types.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" -#include "qom/object.h" -#include "hw/core/cpu.h" #include "hw/registerfields.h" #define NUM_PREGS 4 @@ -36,18 +35,8 @@ #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 -#define TYPE_HEXAGON_CPU "hexagon-cpu" - -#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU -#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU -#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") -#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") -#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") -#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") -#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") - void hexagon_cpu_list(void); #define cpu_list hexagon_cpu_list @@ -127,8 +116,6 @@ typedef struct CPUArchState { VTCMStoreLog vtcm_log; } CPUHexagonState; -OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) - typedef struct HexagonCPUClass { CPUClass parent_class;