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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jf4-20020a170903268400b001ca21e05c69sm629150plb.109.2023.10.16.23.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 23:13:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 32/90] target/sparc: Move UMUL, SMUL to decodetree Date: Mon, 16 Oct 2023 23:11:46 -0700 Message-Id: <20231017061244.681584-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231017061244.681584-1-richard.henderson@linaro.org> References: <20231017061244.681584-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 23 +++++------------------ 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d9474d2a20..c114a13f1d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -172,5 +172,9 @@ XORNcc 10 ..... 010111 ..... . ............. @r_r_ri ADDC 10 ..... 001000 ..... . ............. @r_r_ri ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri MULX 10 ..... 001001 ..... . ............. @r_r_ri +UMUL 10 ..... 001010 ..... . ............. @r_r_ri +UMULcc 10 ..... 011010 ..... . ............. @r_r_ri +SMUL 10 ..... 001011 ..... . ............. @r_r_ri +SMULcc 10 ..... 011011 ..... . ............. @r_r_ri Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b3ce3947f3..b6ec7d5cfd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2859,6 +2859,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) #define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) #define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) #define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) +#define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL) #define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) /* Default case for non jump instructions. */ @@ -4184,6 +4185,8 @@ TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL) TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL) TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl) +TRANS(UMUL, MUL, do_arith, a, gen_op_umul, NULL) +TRANS(SMUL, MUL, do_arith, a, gen_op_smul, NULL) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4193,6 +4196,8 @@ TRANS(SUBcc, ALL, do_cc_arith, a, CC_OP_SUB, gen_op_sub_cc, NULL) TRANS(ANDNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_andc_tl, NULL) TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL) TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL) +TRANS(UMULcc, MUL, do_cc_arith, a, CC_OP_LOGIC, gen_op_umul, NULL) +TRANS(SMULcc, MUL, do_cc_arith, a, CC_OP_LOGIC, gen_op_smul, NULL) static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) { @@ -4655,24 +4660,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { - case 0xa: /* umul */ - CHECK_IU_FEATURE(dc, MUL); - gen_op_umul(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; - case 0xb: /* smul */ - CHECK_IU_FEATURE(dc, MUL); - gen_op_smul(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; case 0xc: /* subx, V9 subc */ gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, (xop & 0x10));