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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.52.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:52:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 32/61] target/hppa: Decode d for cmpclr instructions Date: Wed, 18 Oct 2023 14:51:06 -0700 Message-Id: <20231018215135.1561375-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 ++++-- target/hppa/translate.c | 11 +++++------ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 03b1a11cac..d4a03b0299 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -64,6 +64,7 @@ &rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh &rri_cf t r i cf +&rri_cf_d t r i cf d &rrb_c_f disp n c f r1 r2 &rib_c_f disp n c f r i @@ -78,6 +79,7 @@ @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=%lowsign_11 +@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=%lowsign_11 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=%assemble_12 @@ -158,7 +160,7 @@ or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf -cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf +cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d @@ -189,7 +191,7 @@ addi_tc_tsv 101100 ..... ..... .... 1 ........... @rri_cf subi 100101 ..... ..... .... 0 ........... @rri_cf subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf -cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf +cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d #### # Index Mem diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ed00b58fbc..58d69cb748 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1364,11 +1364,10 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) } static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf) + TCGv_reg in2, unsigned cf, bool d) { TCGv_reg dest, sv; DisasCond cond; - bool d = false; dest = tcg_temp_new(); tcg_gen_sub_reg(dest, in1, in2); @@ -2737,7 +2736,7 @@ static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) return do_log_reg(ctx, a, tcg_gen_xor_reg); } -static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) { TCGv_reg tcg_r1, tcg_r2; @@ -2746,7 +2745,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) } tcg_r1 = load_gpr(ctx, a->r1); tcg_r2 = load_gpr(ctx, a->r2); - do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); + do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d); return nullify_end(ctx); } @@ -2904,7 +2903,7 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_rri_cf *a) return do_sub_imm(ctx, a, true); } -static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) +static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a) { TCGv_reg tcg_im, tcg_r2; @@ -2914,7 +2913,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) tcg_im = tcg_constant_reg(a->i); tcg_r2 = load_gpr(ctx, a->r); - do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); + do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d); return nullify_end(ctx); }