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[5/7] target/rx: Use tcg_gen_ext_i32

Message ID 20231019182921.1772928-6-richard.henderson@linaro.org
State Superseded
Headers show
Series tcg: Expose tcg_gen_ext_{i32,i64,tl} | expand

Commit Message

Richard Henderson Oct. 19, 2023, 6:29 p.m. UTC
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/rx/translate.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

Comments

Philippe Mathieu-Daudé Oct. 19, 2023, 9:54 p.m. UTC | #1
On 19/10/23 20:29, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/rx/translate.c | 11 +++--------
>   1 file changed, 3 insertions(+), 8 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Yoshinori Sato Oct. 21, 2023, 1:45 p.m. UTC | #2
On Fri, 20 Oct 2023 03:29:19 +0900,
Richard Henderson wrote:
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>

> ---
>  target/rx/translate.c | 11 +++--------
>  1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/target/rx/translate.c b/target/rx/translate.c
> index f8860830ae..c6ce717a95 100644
> --- a/target/rx/translate.c
> +++ b/target/rx/translate.c
> @@ -492,13 +492,11 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
>  /* mov.<bwl> rs,rd */
>  static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
>  {
> -    static void (* const mov[])(TCGv ret, TCGv arg) = {
> -        tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32,
> -    };
>      TCGv tmp, mem, addr;
> +
>      if (a->lds == 3 && a->ldd == 3) {
>          /* mov.<bwl> rs,rd */
> -        mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
> +        tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN);
>          return true;
>      }
>  
> @@ -570,10 +568,7 @@ static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a)
>  /* movu.<bw> rs,rd */
>  static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a)
>  {
> -    static void (* const ext[])(TCGv ret, TCGv arg) = {
> -        tcg_gen_ext8u_i32, tcg_gen_ext16u_i32,
> -    };
> -    ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
> +    tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz);
>      return true;
>  }
>  
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/target/rx/translate.c b/target/rx/translate.c
index f8860830ae..c6ce717a95 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -492,13 +492,11 @@  static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
 /* mov.<bwl> rs,rd */
 static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
 {
-    static void (* const mov[])(TCGv ret, TCGv arg) = {
-        tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32,
-    };
     TCGv tmp, mem, addr;
+
     if (a->lds == 3 && a->ldd == 3) {
         /* mov.<bwl> rs,rd */
-        mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
+        tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz | MO_SIGN);
         return true;
     }
 
@@ -570,10 +568,7 @@  static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a)
 /* movu.<bw> rs,rd */
 static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a)
 {
-    static void (* const ext[])(TCGv ret, TCGv arg) = {
-        tcg_gen_ext8u_i32, tcg_gen_ext16u_i32,
-    };
-    ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]);
+    tcg_gen_ext_i32(cpu_regs[a->rd], cpu_regs[a->rs], a->sz);
     return true;
 }