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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id u7-20020aa78487000000b00694fee1011asm1946775pfn.208.2023.10.20.13.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 13:47:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v2 59/65] target/hppa: Fix interruption based on default PSW Date: Fri, 20 Oct 2023 13:43:25 -0700 Message-Id: <20231020204331.139847-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020204331.139847-1-richard.henderson@linaro.org> References: <20231020204331.139847-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Helge Deller The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/int_helper.c | 18 ++++++++++++++---- 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c9a9b9d3be..4aea46442a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -124,6 +124,8 @@ #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ #define CR_RC 0 +#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ +#define PDC_PSW_WIDE_BIT 2 #define CR_PID1 8 #define CR_PID2 9 #define CR_PID3 12 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index f355c4c76b..a11d607b31 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,17 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu = opaque; - int le_bit = ~data & 31; + CPUHPPAState *env = &cpu->env; + int widthm1 = 31; + int le_bit; - cpu->env.cr[CR_EIRR] |= (target_ulong)1 << le_bit; + /* The default PSW.W controls the width of EIRR. */ + if (hppa_is_pa20(env) && env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { + widthm1 = 63; + } + le_bit = ~data & widthm1; + + env->cr[CR_EIRR] |= 1ull << le_bit; eval_interrupt(cpu); } @@ -104,8 +112,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 1 */ env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env); - /* step 2 -- note PSW_W == 0 for !HPPA64. */ - cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0)); + /* step 2 -- Note PSW_W is masked out again for pa1.x */ + cpu_hppa_put_psw(env, + (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W : 0) | + (i == EXCP_HPMC ? PSW_M : 0)); /* step 3 */ env->cr[CR_IIASQ] = iasq_f >> 32;