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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/29] tcg/riscv: Support TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:14:11 -0700 Message-Id: <20231026001542.1141412-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 34e10e77d9..3997e2f274 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -798,8 +798,14 @@ static const struct { static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, TCGReg arg2, TCGLabel *l) { - RISCVInsn op = tcg_brcond_to_riscv[cond].op; + RISCVInsn op; + if (is_tst_cond(cond)) { + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP0, arg1, arg2); + cond = tcg_tst_eqne_cond(cond); + } + + op = tcg_brcond_to_riscv[cond].op; tcg_debug_assert(op != 0); if (tcg_brcond_to_riscv[cond].swap) { @@ -827,6 +833,7 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, case TCG_COND_GEU: /* -> LTU */ case TCG_COND_GT: /* -> LE */ case TCG_COND_GTU: /* -> LEU */ + case TCG_COND_TSTEQ: /* -> TSTNE */ cond = tcg_invert_cond(cond); flags ^= SETCOND_INV; break; @@ -886,6 +893,15 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, } break; + case TCG_COND_TSTNE: + flags |= SETCOND_NEZ; + if (c2) { + tcg_out_opc_imm(s, OPC_ANDI, ret, arg1, arg2); + } else { + tcg_out_opc_reg(s, OPC_AND, ret, arg1, arg2); + } + break; + case TCG_COND_LT: if (c2) { tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2); @@ -1079,7 +1095,7 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, int tmpflags; TCGReg t; - if (!have_zicond && (!c_cmp2 || cmp2 == 0)) { + if (!have_zicond && (!c_cmp2 || cmp2 == 0) && !is_tst_cond(cond)) { tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, val1, c_val1, val2, c_val2); return;