diff mbox series

[v3,30/88] target/hppa: Mask inputs in copy_iaoq_entry

Message ID 20231102013016.369010-31-richard.henderson@linaro.org
State Superseded
Headers show
Series target/hppa: Implement hppa64 cpu | expand

Commit Message

Richard Henderson Nov. 2, 2023, 1:29 a.m. UTC 
Ensure that the destination is always a valid GVA offset.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/translate.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index c2db2782f4..cf05d8b6e4 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -720,10 +720,22 @@  static target_ureg gva_offset_mask(DisasContext *ctx)
 static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest,
                             target_ureg ival, TCGv_reg vval)
 {
-    if (unlikely(ival == -1)) {
+    target_ureg mask = gva_offset_mask(ctx);
+
+    if (ival != -1) {
+        tcg_gen_movi_reg(dest, ival & mask);
+        return;
+    }
+    tcg_debug_assert(vval != NULL);
+
+    /*
+     * We know that the IAOQ is already properly masked.
+     * This optimization is primarily for "iaoq_f = iaoq_b".
+     */
+    if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) {
         tcg_gen_mov_reg(dest, vval);
     } else {
-        tcg_gen_movi_reg(dest, ival);
+        tcg_gen_andi_reg(dest, vval, mask);
     }
 }