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[PULL,04/85] target/hppa: Always report one page to tlb_set_page

Message ID 20231107030407.8979-5-richard.henderson@linaro.org
State Accepted
Commit f8cda28b8dd6f9d52042a3d45558de81e4c54e36
Headers show
Series [PULL,01/85] target/hppa: Include PSW_P in tb flags and mmu index | expand

Commit Message

Richard Henderson Nov. 7, 2023, 3:02 a.m. UTC 
No need to trigger the large_page_mask code unnecessarily.
Drop the now unused HPPATLBEntry.page_size field.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/hppa/cpu.h        |  5 +++--
 target/hppa/mem_helper.c | 11 +++++++++--
 2 files changed, 12 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 84bb6edc60..1480d0237a 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -179,15 +179,16 @@  typedef struct HPPATLBEntry {
     IntervalTreeNode itree;
 
     target_ureg pa;
+
+    unsigned entry_valid : 1;
+
     unsigned u : 1;
     unsigned t : 1;
     unsigned d : 1;
     unsigned b : 1;
-    unsigned page_size : 4;
     unsigned ar_type : 3;
     unsigned ar_pl1 : 2;
     unsigned ar_pl2 : 2;
-    unsigned entry_valid : 1;
     unsigned access_id : 16;
 } HPPATLBEntry;
 
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 687ae44ed0..60cae646cc 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -268,9 +268,16 @@  bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
 
     trace_hppa_tlb_fill_success(env, addr & TARGET_PAGE_MASK,
                                 phys & TARGET_PAGE_MASK, size, type, mmu_idx);
-    /* Success!  Store the translation into the QEMU TLB.  */
+
+    /*
+     * Success!  Store the translation into the QEMU TLB.
+     * Note that we always install a single-page entry, because that
+     * is what works best with softmmu -- anything else will trigger
+     * the large page protection mask.  We do not require this,
+     * because we record the large page here in the hppa tlb.
+     */
     tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
-                 prot, mmu_idx, TARGET_PAGE_SIZE << (ent ? 2 * ent->page_size : 0));
+                 prot, mmu_idx, TARGET_PAGE_SIZE);
     return true;
 }